53a1a29a92
commit 218bbea11a777c156eb7bcbdc72867b32ae10985 upstream. Add support for the four-port variant of the Qualcomm QCA833x switch. The CPU port default link settings can be reconfigured using a fixed-link sub-node. Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
110 lines
2.1 KiB
Text
110 lines
2.1 KiB
Text
* Qualcomm Atheros QCA8xxx switch family
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Required properties:
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- compatible: should be one of:
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"qca,qca8334"
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"qca,qca8337"
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- #size-cells: must be 0
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- #address-cells: must be 1
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Subnodes:
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The integrated switch subnode should be specified according to the binding
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described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of
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port and PHY id, each subnode describing a port needs to have a valid phandle
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referencing the internal PHY connected to it. The CPU port of this switch is
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always port 0.
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A CPU port node has the following optional node:
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- fixed-link : Fixed-link subnode describing a link to a non-MDIO
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managed entity. See
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Documentation/devicetree/bindings/net/fixed-link.txt
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for details.
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For QCA8K the 'fixed-link' sub-node supports only the following properties:
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- 'speed' (integer, mandatory), to indicate the link speed. Accepted
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values are 10, 100 and 1000
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- 'full-duplex' (boolean, optional), to indicate that full duplex is
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used. When absent, half duplex is assumed.
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Example:
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&mdio0 {
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phy_port1: phy@0 {
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reg = <0>;
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};
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phy_port2: phy@1 {
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reg = <1>;
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};
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phy_port3: phy@2 {
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reg = <2>;
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};
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phy_port4: phy@3 {
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reg = <3>;
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};
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phy_port5: phy@4 {
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reg = <4>;
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};
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switch0@0 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&gmac1>;
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phy-mode = "rgmii";
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fixed-link {
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speed = 1000;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&phy_port1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&phy_port2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&phy_port3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&phy_port4>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&phy_port5>;
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};
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};
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};
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};
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