650321fe96
commit 38c0a74fe06da3be133cae3fb7bde6a9438e698b upstream. The MIPS implementation of pci_resource_to_user() introduced in v3.12 by commit4c2924b725("MIPS: PCI: Use pci_resource_to_user to map pci memory space properly") incorrectly sets *end to the address of the byte after the resource, rather than the last byte of the resource. This results in userland seeing resources as a byte larger than they actually are, for example a 32 byte BAR will be reported by a tool such as lspci as being 33 bytes in size: Region 2: I/O ports at 1000 [disabled] [size=33] Correct this by subtracting one from the calculated end address, reporting the correct address to userland. Signed-off-by: Paul Burton <paul.burton@mips.com> Reported-by: Rui Wang <rui.wang@windriver.com> Fixes:4c2924b725("MIPS: PCI: Use pci_resource_to_user to map pci memory space properly") Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v3.12+ Patchwork: https://patchwork.linux-mips.org/patch/19829/ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <asm/cpu-info.h>
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unsigned long PCIBIOS_MIN_IO;
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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unsigned long PCIBIOS_MIN_MEM;
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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static int __init pcibios_set_cache_line_size(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the highest level in the
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* cache hierarchy.
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*/
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lsize = c->dcache.linesz;
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lsize = c->scache.linesz ? : lsize;
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lsize = c->tcache.linesz ? : lsize;
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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return 0;
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}
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arch_initcall(pcibios_set_cache_line_size);
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void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc, resource_size_t *start,
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resource_size_t *end)
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{
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phys_addr_t size = resource_size(rsrc);
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*start = fixup_bigphys_addr(rsrc->start, size);
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*end = rsrc->start + size - 1;
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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prot = pgprot_val(vma->vm_page_prot);
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prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
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vma->vm_page_prot = __pgprot(prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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}
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