perf, x86: Improve the PEBS ABI
Rename perf_event_attr::precise to perf_event_attr::precise_ip and widen it to 2 bits. This new field describes the required precision of the PERF_SAMPLE_IP field: 0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid And modify the Intel PEBS code accordingly. The PEBS implementation now supports up to precise_ip == 2, where we perform the IP fixup. Also s/PERF_RECORD_MISC_EXACT/&_IP/ to clarify its meaning, this bit should be set for each PERF_SAMPLE_IP field known to match the actual instruction triggering the event. This new scheme allows for a PEBS mode that uses the buffer for more than a single event. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Stephane Eranian <eranian@google.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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6 changed files with 59 additions and 22 deletions
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@ -203,9 +203,19 @@ struct perf_event_attr {
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enable_on_exec : 1, /* next exec enables */
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task : 1, /* trace fork/exit */
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watermark : 1, /* wakeup_watermark */
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precise : 1, /* OoO invariant counter */
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/*
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* precise_ip:
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*
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* 0 - SAMPLE_IP can have arbitrary skid
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* 1 - SAMPLE_IP must have constant skid
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* 2 - SAMPLE_IP requested to have 0 skid
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* 3 - SAMPLE_IP must have 0 skid
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*
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* See also PERF_RECORD_MISC_EXACT_IP
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*/
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precise_ip : 2, /* skid constraint */
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__reserved_1 : 48;
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__reserved_1 : 47;
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union {
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__u32 wakeup_events; /* wakeup every n events */
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@ -296,7 +306,12 @@ struct perf_event_mmap_page {
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#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
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#define PERF_RECORD_MISC_GUEST_USER (5 << 0)
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#define PERF_RECORD_MISC_EXACT (1 << 14)
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/*
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* Indicates that the content of PERF_SAMPLE_IP points to
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* the actual instruction that triggered the event. See also
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* perf_event_attr::precise_ip.
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*/
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#define PERF_RECORD_MISC_EXACT_IP (1 << 14)
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/*
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* Reserve the last bit to indicate some extended misc field
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*/
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