Merge branches 'pci/enumeration' and 'pci/misc' into next
* pci/enumeration: PCI: Set MPS to match upstream bridge PCI: Move MPS configuration check to pci_configure_device() PCI: Drop references acquired by of_parse_phandle() PCI/MSI: Remove unused pcibios_msi_controller() hook ARM/PCI: Remove msi_controller from struct pci_sys_data ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi() PCI: Add pci_scan_root_bus_msi() ARM/PCI: Replace panic with WARN messages on failures PCI: generic: Add arm64 support PCI: Build setup-irq.o for arm64 PCI: generic: Remove dependency on ARM-specific struct hw_pci ARM/PCI: Set MPS before pci_bus_add_devices() * pci/misc: PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI
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commit
9ca678d1df
16 changed files with 149 additions and 130 deletions
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@ -744,10 +744,11 @@ struct pci_driver {
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void pcie_bus_configure_settings(struct pci_bus *bus);
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enum pcie_bus_config_types {
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PCIE_BUS_TUNE_OFF,
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PCIE_BUS_SAFE,
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PCIE_BUS_PERFORMANCE,
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PCIE_BUS_PEER2PEER,
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PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
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PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
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PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
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PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
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PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
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};
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extern enum pcie_bus_config_types pcie_bus_config;
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@ -793,6 +794,10 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
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int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
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int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
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void pci_bus_release_busn_res(struct pci_bus *b);
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struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
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struct pci_ops *ops, void *sysdata,
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struct list_head *resources,
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struct msi_controller *msi);
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struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
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struct pci_ops *ops, void *sysdata,
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struct list_head *resources);
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