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import G965FXXU7DTAA OSRC

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*First release for Android (Q).

Signed-off-by: FAROVITUS <farovitus@gmail.com>
This commit is contained in:
FAROVITUS 2020-02-04 13:44:48 +02:00
parent 856452b4f2
commit 2b92eefa41
7696 changed files with 3763754 additions and 92661 deletions
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111
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#Android makefile to build kernel as a part of Android Build
ifeq ($(KERNEL_DEFCONFIG),)
$(error KERNEL_DEFCONFIG must be set as environment variable)
endif
ifeq ($(INSTALLED_KERNEL_TARGET),)
INSTALLED_KERNEL_TARGET := $(PRODUCT_OUT)/kernel
INSTALLED_DTBOIMAGE_TARGET := $(PRODUCT_OUT)/dtbo.img
BOARD_PREBUILT_DTBOIMAGE := $(PRODUCT_OUT)/prebuilt_dtbo.img
INSTALLED_DTB_TARGET := $(PRODUCT_OUT)/dtb.img
endif
TARGET_KERNEL_ARCH := $(strip $(TARGET_KERNEL_ARCH))
ifeq ($(TARGET_KERNEL_ARCH),)
KERNEL_ARCH := arm64
else
KERNEL_ARCH := $(TARGET_KERNEL_ARCH)
endif
ifeq ($(CROSS_COMPILE),)
KERNEL_CROSS_COMPILE := aarch64-linux-android-
else
KERNEL_CROSS_COMPILE := $(CROSS_COMPILE)
endif
# SOONG_GLOBAL_CONFIG := build/soong/cc/config/global.go
# CLANG_VERSION := $(shell grep "ClangDefaultVersion" $(SOONG_GLOBAL_CONFIG) | grep -o "clang-[0-9][0-9]*")
# CLANG_PATH := prebuilts/clang/host/linux-x86
# CC :=$(PWD)/$(CLANG_PATH)/$(CLANG_VERSION)/bin/clang
# ifeq ($(CLANG_TRIPLE),)
# CLANG_TRIPLE := aarch64-linux-gnu-
# else
# CLANG_TRIPLE := $(CLANG_TRIPLE)
# endif
ifeq ($(TARGET_PREBUILT_KERNEL),)
TARGET_KERNEL_SOURCE := kernel/$(TARGET_KERNEL)
KERNEL_CONFIG := $(TARGET_KERNEL_SOURCE)/.config
KERNEL_BOOT := $(TARGET_KERNEL_SOURCE)/arch/$(KERNEL_ARCH)/boot
KERNEL_BIN := $(KERNEL_BOOT)/Image
KERNEL_DTB_DIR := $(KERNEL_BOOT)/dts/exynos
ifeq ($(TARGET_USE_EVT0),true)
KERNEL_DTB := $(KERNEL_DTB_DIR)/$(TARGET_SOC)_evt0.dtb
KERNEL_DTBO_CFG := $(KERNEL_DTB_DIR)/$(TARGET_SOC)_evt0_dtboimg.cfg
else
KERNEL_DTB := $(KERNEL_DTB_DIR)/$(TARGET_SOC).dtb
KERNEL_DTBO_CFG := $(KERNEL_DTB_DIR)/$(TARGET_SOC)_dtboimg.cfg
endif
MKDTIMG := $(HOST_OUT_EXECUTABLES)/mkdtimg
KERNEL_MERGE_CONFIG := $(TARGET_KERNEL_SOURCE)/scripts/kconfig/merge_config.sh
KERNEL_CONFIG_BASE := $(TARGET_KERNEL_SOURCE)/arch/$(KERNEL_ARCH)/configs
KERNEL_DEFCONFIG_PATH := $(KERNEL_CONFIG_BASE)/$(KERNEL_DEFCONFIG)
KERNEL_USER_CFG := $(KERNEL_CONFIG_BASE)/$(TARGET_SOC)_user.cfg
KERNEL_USERDEBUG_CFG := $(KERNEL_CONFIG_BASE)/$(TARGET_SOC)_userdebug.cfg
ifeq ($(KERNEL_DEFCONFIG),)
$(error Kernel configuration not defined, cannot build kernel)
else
ifeq ($(TARGET_BUILD_VARIANT),eng)
MAKE_CONFIG_CMD := $(MAKE) -C $(TARGET_KERNEL_SOURCE) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(KERNEL_DEFCONFIG)
else
ifeq ($(TARGET_BUILD_VARIANT),userdebug)
MAKE_CONFIG_CMD := ARCH=$(KERNEL_ARCH) $(KERNEL_MERGE_CONFIG) -m -O $(TARGET_KERNEL_SOURCE) $(KERNEL_DEFCONFIG_PATH) $(KERNEL_USERDEBUG_CFG);
MAKE_CONFIG_CMD += $(MAKE) -C $(TARGET_KERNEL_SOURCE) ARCH=$(KERNEL_ARCH) KCONFIG_ALLCONFIG=.config alldefconfig
else
MAKE_CONFIG_CMD := ARCH=$(KERNEL_ARCH) $(KERNEL_MERGE_CONFIG) -m -O $(TARGET_KERNEL_SOURCE) $(KERNEL_DEFCONFIG_PATH) $(KERNEL_USER_CFG);
MAKE_CONFIG_CMD += $(MAKE) -C $(TARGET_KERNEL_SOURCE) ARCH=$(KERNEL_ARCH) KCONFIG_ALLCONFIG=.config alldefconfig
endif
endif
ifeq ($(N_KERNEL_BUILD_THREAD),)
N_KERNEL_BUILD_THREAD := 1
endif
TARGET_PREBUILT_KERNEL := $(KERNEL_BIN)
.PHONY: phony-rebuild
.PHONY: kernel
kernel: $(KERNEL_BIN)
.PHONY: kernel-distclean
kernel-distclean:
$(MAKE) -C $(TARGET_KERNEL_SOURCE) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) distclean
$(KERNEL_CONFIG): phony-rebuild
$(hide) echo "make $(KERNEL_DEFCONFIG)"
$(MAKE_CONFIG_CMD)
$(KERNEL_BIN): $(KERNEL_CONFIG)
$(hide) echo "Building kernel..."
$(MAKE) -C $(TARGET_KERNEL_SOURCE) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) -j$(N_KERNEL_BUILD_THREAD)
$(INSTALLED_KERNEL_TARGET): $(INSTALLED_DTBOIMAGE_TARGET)
cp $(KERNEL_BIN) $(INSTALLED_KERNEL_TARGET)
cp $(KERNEL_DTB) $(INSTALLED_DTB_TARGET)
$(BOARD_PREBUILT_DTBOIMAGE): $(MKDTIMG) $(KERNEL_DTBO_CFG) $(KERNEL_BIN)
$(hide) echo "Building DTBOIMAGE..."
ln -sf $(TARGET_KERNEL_SOURCE)/arch
$(MKDTIMG) cfg_create $@ $(KERNEL_DTBO_CFG)
rm -f arch
endif #TARGET_PREBUILT_KERNEL
endif #KERNEL_DEFCONFIG

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What: /proc/uid_concurrent_active_time
Date: December 2018
Contact: Connor O'Brien <connoro@google.com>
Description:
The /proc/uid_concurrent_active_time file displays aggregated cputime
numbers for each uid, broken down by the total number of cores that were
active while the uid's task was running.
What: /proc/uid_concurrent_policy_time
Date: December 2018
Contact: Connor O'Brien <connoro@google.com>
Description:
The /proc/uid_concurrent_policy_time file displays aggregated cputime
numbers for each uid, broken down based on the cpufreq policy
of the core used by the uid's task and the number of cores associated
with that policy that were active while the uid's task was running.

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What: /proc/pid/smaps_rollup
Date: August 2017
Contact: Daniel Colascione <dancol@google.com>
Description:
This file provides pre-summed memory information for a
process. The format is identical to /proc/pid/smaps,
except instead of an entry for each VMA in a process,
smaps_rollup has a single entry (tagged "[rollup]")
for which each field is the sum of the corresponding
fields from all the maps in /proc/pid/smaps.
For more details, see the procfs man page.
Typical output looks like this:
00100000-ff709000 ---p 00000000 00:00 0 [rollup]
Rss: 884 kB
Pss: 385 kB
Shared_Clean: 696 kB
Shared_Dirty: 0 kB
Private_Clean: 120 kB
Private_Dirty: 68 kB
Referenced: 884 kB
Anonymous: 68 kB
LazyFree: 0 kB
AnonHugePages: 0 kB
ShmemPmdMapped: 0 kB
Shared_Hugetlb: 0 kB
Private_Hugetlb: 0 kB
Swap: 0 kB
SwapPss: 0 kB
Locked: 385 kB

1
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vrl4

153
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Cirrus Logic Madera class audio codecs extcon driver
The extcon configuration settings are a child node of the parent MFD driver
binding.
See Documentation/devicetree/bindings/mfd/madera.txt
This node contains one or more child nodes to describe the configuration for
each accessory detect.
Mandatory properties:
- compatible : must be "cirrus,madera-extcon"
- #address-cells : must be 1
- #size-cells : must be 0
Optional properties:
- cirrus,gpsw : Settings for the general purpose switches, set as per the
SWn_MODE bits in the GP Switch 1 register. If given must be 2 cells.
First cell is the value for the SW1_MODE
Second cell is the value for the SW2_MODE (cs47l90, cs47l91)
- cirrus,micd-pol-gpios : GPIO specifier for the GPIO controlling the headset
polarity if one exists. One cell for each child node.
Child node mandatory properties:
- reg : output number this configuration applies to, must be 1
Child node optional properties:
- cirrus,micd-detect-debounce-ms : Additional software microphone detection
debounce specified in milliseconds
- cirrus,micd-manual-debounce : Additional software button detection
debounce specified as a number
- cirrus,micd-bias-start-time : Time allowed for MICBIAS to startup prior to
performing microphone detection, specified as per the MICD_BIAS_STARTTIME
bits in the register MIC_DETECT_1
- cirrus,micd-rate : Delay between successive microphone detection
measurements, specified as per the MICD_RATE bits in the register
MIC_DETECT_1
- cirrus,micd-dbtime : Microphone detection hardware debounce level, specified
as per the MICD_DBTIME bits in the register MIC_DETECT_1
- cirrus,micd-timeout-ms : Timeout for microphone detection, specified in
milliseconds
- cirrus,micd-force-micbias : Force MICBIAS continuously on during microphone
detection and button detection
- cirrus,micd-software-compare : Use a software comparison to determine mic
presence
- cirrus,jd-invert : Invert the polarity of the jack detection switch
- cirrus,jd-use-jd2 : Use JD2 input with JD1 for dual jack detection.
- cirrus,fixed-hpdet-imp : Do not perform any headphone detection, just use
the fixed value specified here as the headphone impedance. Value is in
hundredths-of-an-ohm (ohms * 100)
- cirrus,hpdet-ext-res : Impedance of external series resistor on hpdet.
Value is in hundredths-of-an-ohm (ohms * 100)
- cirrus,hpdet-short-circuit-imp : Specifies the maximum impedance in ohms
that will be considered as a short circuit
- cirrus,hpdet-channel : Set which channel is used for headphone impedance
measurement. 0 = left, 1 = right
- cirrus,micd-clamp-mode : Specifies the logic of the micdetect clamp block
- cirrus,hpd-pins : 4 cells specifying the clamp and sense pins to use.
<clamp_left sense_left clamp_right sense_right>
where clamp_x is the clamp pin for channel x and sense_x is the impedance
sense pin for channel x, as per the HPD_OUT_SEL field of HEADPHONE_DETECT_0
register. A value >0xFFFF means use the default.
(cs47l90, cs47l91)
- cirrus,micd-ranges : Microphone detection level and key configuration, this
field can be of variable length but should always be a multiple of 2 cells
long, each two cell group represents one button configuration
The first cell is the maximum impedance for this button in ohms
The second cell the key that should be reported to the input layer
- cirrus,micd-configs : Headset polarity configurations, variable length but
must be a multiple of 5 cells, each 5-cell group represents one
polarity configuration
first cell is the value of
ACCDET_SRC register field (CS47L35, CS47L85, WM1840),
MICD_SENSE_SEL register field (all other codecs)
second cell is the accessory detection ground as per the MICD_GND_SEL
register field
the third cell is the MICBIAS to be used as per the MICD_BIAS_SRC register
field
fourth cell is the value of the micd-pol-gpio pin, a non-zero value
indicates this should be on
fifth cell is
set to zero (cs47l35, cs47l85, wm1840)
value of HPn_GND_SEL register field (all other codecs)
- cirrus,init-delay-ms : Add a delay after jack detection (in milliseconds)
- cirrus,hs-mic: Specify an input to mute during headset button presses:
1 - IN1L, 2 - IN1R, ..., n - IN[n]R
- cirrus,moisture-pin : The pin on which the moisture detection should be
run. For (cs47l35, cs47l85, wm1840) this should be set to
MADERA_ACCDET_MODE_HPx, for (cs47l90, cs47l91) this should be set to
MADERA_HPD_SENSE_x.
- cirrus,moisture-imp : The impedance threshold above which a detection will
be considered moisture rather than a valid jack detection.
- cirrus,moisture-debounce : The number of debounce measurements to perform
on the moisture detection.
Example:
codec: cs47l85@0 {
compatible = "cirrus,cs47l85";
accdet {
compatible = "cirrus,madera-extcon";
#address-cells = <1>;
#size-cells = <0>;
cirrus,gpsw = <3 0>;
cirrus,micd-pol-gpios = <&gpio 0>
acc@1 {
reg = <1>;
cirrus,micd-detect-debounce-ms = <10>;
cirrus,micd-bias-start-time = <0x1>;
cirrus,micd-rate = <0x1>;
cirrus,micd-dbtime = <0x1>;
cirrus,micd-timeout-ms = <10>;
cirrus,micd-force-micbias;
cirrus,micd-ranges = <
11 0x100
28 0x101
54 0x102
100 0x103
186 0x104
430 0x105
>;
cirrus,micd-configs = <
0x1 0 1 0 2
0x0 0 2 1 2
>;
};
};
};

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Cirrus Logic Madera class audio codecs gpio driver
These codecs have a set of configurable GPIO pins. The bindings here configure
the driver that provides access to these GPIOs.
See also
- the core bindings for the parent MFD driver:
See Documentation/devicetree/bindings/mfd/madera.txt
- the pinctrl bindings for these codecs
See Documentation/devicetree/bindings/pinctrl/cirrus,madera-pinctrl.txt
Required properties:
- compatible : must be "cirrus,madera-gpio"
- gpio-controller : Indicates this device is a GPIO controller.
- #gpio-cells : Must be 2. The first cell is the pin number. The second cell
is reserved for future use and must be zero
Optional properties:
- gpio-line-names : as described in bindings/gpio/gpio.txt
Example:
cs47l85@0 {
compatible = "cirrus,cs47l85";
gpio-controller;
#gpio-cells = <2>;
};

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MELFAS FTS Touchscreen
Required properties:
- compatible: must be "stm,fts_touch"
- reg: I2C slave address of the chip (0x48)
- interrupt-parent: interrupt controller to which the chip is connected
- interrupts: interrupt to which the chip is connected
Example:
hsi2c_23: hsi2c@108E0000 {
status = "okay";
samsung,reset-before-trans;
touchscreen@49 {
compatible = "stm,fts_touch";
reg = <0x49>;
pinctrl-names = "on_state", "off_state";
pinctrl-0 = <&attn_irq>;
pinctrl-1 = <&attn_input>;
stm,tspid_gpio = <&gpe6 5 0>;
stm,irq_gpio = <&gpa1 0 0>;
stm,irq_type = <8200>;
stm,num_lines = <32 16>; /* rx tx */
stm,max_coords = <1439 2959>; /* x y */
stm,grip_area = <512>;
stm,regulator_dvdd = "vdd3";
stm,regulator_avdd = "vdd5";
stm,project_name = "Dream2", "G955";
stm,firmware_name = "tsp_stm/fts8cd56_dream2.fw", "tsp_stm/fts8cd56_dream2.fw";
stm,support_gesture = <1>;
};
};

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Cirrus Logic Madera class audio codecs pinctrl driver
The Cirrus Logic Madera codecs provide a number of GPIO functions for
interfacing to external hardware and to provide logic outputs to other devices.
Certain groups of GPIO pins also have an alternate function, normally as an
audio interface.
The set of available GPIOs, functions and alternate function groups differs
between codecs so refer to the datasheet for the codec for further information
on what is supported on that device.
The properties for this driver exist within the parent MFD driver node.
See also
the core bindings for the parent MFD driver:
Documentation/devicetree/bindings/mfd/madera.txt
the generic pinmix bindings:
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Required properties of parent mfd node:
- pinctrl-names : must be "default"
- pinctrl-0 : a phandle to the node containing the subnodes containing default
configurations
Required subnodes:
One subnode is required to contain the default settings. It contains an
arbitrary number of configuration subnodes, one for each group or pin
configuratio you want to apply as a default.
Required properties of configuration subnodes:
- groups : name of one pin group to configure. One of:
aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2,
dmic4, dmic5, dmic6,
gpio1, gpio2, ..., gpio40
The gpioN groups select the single pin of this name for configuration
Optional properties of configuration subnodes:
Any configuration option not explicitly listed in the dts will be left at
chip default setting.
- function : name of function to assign to this group. One of:
aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2,
dmic3, dmic4, dmic5, dmic6,
io, dsp-gpio, irq1, irq2,
fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock,
fllao-clk, fllao-lock,
opclk, opclk-async, pwm1, pwm2, spdif,
asrc1-in1-lock, asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock,
spkl-short-circuit, spkr-short-circuit, spk-shutdown,
spk-overheat-shutdown, spk-overheat-warn,
timer1-sts, timer2-sts, timer3-sts, timer4-sts, timer5-sts, timer6-sts,
timer7-sts, timer8-sts,
log1-fifo-ne, log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, log5-fifo-ne,
log6-fifo-ne, log7-fifo-ne, log8-fifo-ne,
- bias-disable : disable pull-up and pull-down
- bias-bus-hold : enable buskeeper
- bias-pull-up : output is pulled-up
- bias-pull-down : output is pulled-down
- drive-push-pull : CMOS output
- drive-open-drain : open-drain output
- drive-strength : drive strength in mA. Valid values are 4 or 8
- input-schmitt-enable : enable schmitt-trigger mode
- input-schmitt-disable : disable schmitt-trigger mode
- input-debounce : A value of 0 disables debounce, a value !=0 enables
debounce
- output-low : set the pin to output mode with low level
- output-high : set the pin to output mode with high level
Example:
cs47l85@0 {
compatible = "cirrus,cs47l85";
pinctrl-names = "default";
pinctrl-0 = <&cs47l85_defaults>;
cs47l85_defaults: cs47l85-gpio-defaults {
aif1 {
groups = "aif1";
function = "aif1";
bias-bus-hold;
};
aif2 {
groups = "aif2";
function = "aif2";
bias-bus-hold;
};
opclk {
groups = "gpio1";
function = "opclk";
bias-pull-up;
drive-strength = <8>;
};
};
};

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* EXYNOS - USI(Universal Serial Interface) devicetree making guide
The USI can operate as UART, HSI2C and SPI.
So the configuration for one specific function
should be needed with SYSREG(System Registers).
To configure USI port as one specific function,
function string(ex, "spi" or "hsi2c0" or "hsi2c1" or "spi" or "uart" or
"hsi2c0_hsi2c1" or "uart_hsi2c1")
should be declared in "usi_mode" property in board devicetree file.
Becuase USI configuration can differ from board schematic.
* Required SoC Specific Properties:
- compatible: should be one of the following.
- samsung,exynos-usi: for exynos7, exynos8 platforms.
- reg: physical base address of the SYSREG for specific USI port
and length of memory mapped region.
* Required Board Specific Properties:
- usi_mode: function string for one specific IP operation.
hsi2c0: for HSI2C0
hsi2c1: for HSI2C1
spi: for SPI
uart: for UART
hsi2c0_hsi2c1: for HSI2C0 and HSI2C1
uart_hsi2c1: for UART(without hardware flow control) and HSI2C1
In case of HSI2C function of USI,
hsi2c0 and hsi2c1 should be declared in according to board schemetic.
If shemetic describes USI pin as "XUSI##_SDA0" and XUSI##_SCL0",
we need to use "hsi2c0" for usi_mode.
If shemetic describes USI pin as "XUSI##_SDA1" and XUSI##_SCL1",
we need to use "hsi2c1" for usi_mode.
If shemetic describes USI pin as "XUSI##_SDA0" and XUSI##_SCL0",
and there is also "XUSI##_SDA1" and XUSI##_SCL1",
we need to use "hsi2c0_hsi2c1" for usi_mode.
* Exsamples:
- SoC Specific Portion
/* USI_0 */
usi_0: usi@10421000 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421000 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_1 */
usi_1: usi@10421004 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421004 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
/* USI_2 */
usi_2: usi@10421008 {
compatible = "samsung,exynos-usi";
reg = <0x0 0x10421008 0x4>;
/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
status = "disabled";
};
- Board Specific Portion
/* USI MODE SETTINGS
usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
or "hsi2c0_hsi2c1" or "uart_hsi2c1"
*/
usi_0: usi@10421000 {
usi_mode = "spi";
status = "okay";
};
usi_1: usi@10421004 {
usi_mode = "spi";
status = "okay";
};
usi_2: usi@10421008 {
usi_mode = "hsi2c0";
status = "okay";
};
If USI configuration was done successfully, the booting log will be shown as below.
[ 0.700485] [1: swapper/0: 1] usi 10421000.usi: usi_probe() mode:4
[ 0.702369] [1: swapper/0: 1] usi 10421004.usi: usi_probe() mode:4
[ 0.704134] [1: swapper/0: 1] usi 10421008.usi: usi_probe() mode:1
This means the usi_0 was set as "spi" and usi_1 was set as "spi" and
usi_2 was set as "hsi2c0".
The mode values are as below.
/* USI mode */
#define USI_HSI2C0_SINGLE_MODE 0x1
#define USI_HSI2C1_SINGLE_MODE 0x2
#define USI_HSI2C0_HSI2C1_DUAL_MODE 0x3
#define USI_SPI_SINGLE_MODE 0x4
#define USI_UART_SINGLE_MODE 0x8
#define USI_UART_HSI2C1_DUAL_MODE 0xA

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* EXYNOS - USI(Universal Serial Interface) version 2 devicetree making guide
The USI can operate as UART, HSI2C and SPI.
So the configuration for one specific function
should be needed with SYSREG(System Registers).
To configure USI port as one specific function,
function string(ex, "spi" or "i2c" or "spi" or "uart")
should be declared in "usi_mode" property in board devicetree file.
Becuase USI configuration can differ from board schematic.
* Required SoC Specific Properties:
- compatible: should be one of the following.
- samsung,exynos-usi-v2: for exynos7, exynos8 platforms.
- reg: physical base address of the SYSREG for specific USI port
and length of memory mapped region.
* Required Board Specific Properties:
- usi_v2_mode: function string for one specific IP operation.
i2c: for HSI2C
spi: for SPI
uart: for UART
* Compare to USI version 1, there are few differences.
- HW I2C has been changed
I2C hw logic has been developed by usi_v2 including timing parameter logic.
HSI2C driver must be upgraded from usi_v2.
- USI structure has been changed.
One USIv2 chanenl is composed of "USI + HSI2C" hw logic.
* Exsamples:
- SoC Specific Portion
/* USI_00 */
usi_0: usi@10411004 {
compatible = "samsung,exynos-usi-v2";
reg = <0x0 0x10411004 0x4>;
/* usi_mode_v2 = "i2c" or "spi" or "uart" */
status = "disabled";
};
/* USI_00_I2C */
usi_0_i2c: usi@10411008 {
compatible = "samsung,exynos-usi-v2";
reg = <0x0 0x10411008 0x4>;
/* usi_mode_v2 = "i2c" */
status = "disabled";
};
- Board Specific Portion
/* USI_00 */
usi_0: usi@10411004 {
usi_v2_mode = "spi";
status = "okay";
};
/* USI_01 */
usi_1: usi@1041100c {
usi_v2_mode = "spi";
status = "okay";
};
/* USI_02 */
usi_2: usi@10411014 {
usi_v2_mode = "spi";
status = "okay";
};
/* USI_03 */
usi_3: usi@1041101C {
usi_v2_mode = "i2c";
status = "okay";
};
If USI configuration was done successfully, the booting log will be shown as below.
[ 1.817710] [7: swapper/0: 1] usi_v2 10411004.usi: usi_v2_probe() mode:2
[ 1.820072] [7: swapper/0: 1] usi_v2 1041100c.usi: usi_v2_probe() mode:2
[ 1.822549] [7: swapper/0: 1] usi_v2 10411014.usi: usi_v2_probe() mode:2
[ 1.825060] [7: swapper/0: 1] usi_v2 1041101c.usi: usi_v2_probe() mode:4
This means the usi_0, usi_1, usi_2 were set as "spi" and usi_3 was set "i2c"
The mode values are as below.
/* USI v2 mode */
#define I2C_SW_CONF (1<<2)
#define SPI_SW_CONF (1<<1)
#define UART_SW_CONF (1<<0)

1
Documentation/devicetree/bindings/vendor-prefixes.txt
View file

@ -314,3 +314,4 @@ zarlink Zarlink Semiconductor
zii Zodiac Inflight Innovations
zte ZTE Corp.
zyxel ZyXEL Communications Corp.
stm STMicroelectronics Corp.

626
Documentation/filesystems/fscrypt.rst
View file

@ -1,626 +0,0 @@
=====================================
Filesystem-level encryption (fscrypt)
=====================================
Introduction
============
fscrypt is a library which filesystems can hook into to support
transparent encryption of files and directories.
Note: "fscrypt" in this document refers to the kernel-level portion,
implemented in ``fs/crypto/``, as opposed to the userspace tool
`fscrypt <https://github.com/google/fscrypt>`_. This document only
covers the kernel-level portion. For command-line examples of how to
use encryption, see the documentation for the userspace tool `fscrypt
<https://github.com/google/fscrypt>`_. Also, it is recommended to use
the fscrypt userspace tool, or other existing userspace tools such as
`fscryptctl <https://github.com/google/fscryptctl>`_ or `Android's key
management system
<https://source.android.com/security/encryption/file-based>`_, over
using the kernel's API directly. Using existing tools reduces the
chance of introducing your own security bugs. (Nevertheless, for
completeness this documentation covers the kernel's API anyway.)
Unlike dm-crypt, fscrypt operates at the filesystem level rather than
at the block device level. This allows it to encrypt different files
with different keys and to have unencrypted files on the same
filesystem. This is useful for multi-user systems where each user's
data-at-rest needs to be cryptographically isolated from the others.
However, except for filenames, fscrypt does not encrypt filesystem
metadata.
Unlike eCryptfs, which is a stacked filesystem, fscrypt is integrated
directly into supported filesystems --- currently ext4, F2FS, and
UBIFS. This allows encrypted files to be read and written without
caching both the decrypted and encrypted pages in the pagecache,
thereby nearly halving the memory used and bringing it in line with
unencrypted files. Similarly, half as many dentries and inodes are
needed. eCryptfs also limits encrypted filenames to 143 bytes,
causing application compatibility issues; fscrypt allows the full 255
bytes (NAME_MAX). Finally, unlike eCryptfs, the fscrypt API can be
used by unprivileged users, with no need to mount anything.
fscrypt does not support encrypting files in-place. Instead, it
supports marking an empty directory as encrypted. Then, after
userspace provides the key, all regular files, directories, and
symbolic links created in that directory tree are transparently
encrypted.
Threat model
============
Offline attacks
---------------
Provided that userspace chooses a strong encryption key, fscrypt
protects the confidentiality of file contents and filenames in the
event of a single point-in-time permanent offline compromise of the
block device content. fscrypt does not protect the confidentiality of
non-filename metadata, e.g. file sizes, file permissions, file
timestamps, and extended attributes. Also, the existence and location
of holes (unallocated blocks which logically contain all zeroes) in
files is not protected.
fscrypt is not guaranteed to protect confidentiality or authenticity
if an attacker is able to manipulate the filesystem offline prior to
an authorized user later accessing the filesystem.
Online attacks
--------------
fscrypt (and storage encryption in general) can only provide limited
protection, if any at all, against online attacks. In detail:
fscrypt is only resistant to side-channel attacks, such as timing or
electromagnetic attacks, to the extent that the underlying Linux
Cryptographic API algorithms are. If a vulnerable algorithm is used,
such as a table-based implementation of AES, it may be possible for an
attacker to mount a side channel attack against the online system.
Side channel attacks may also be mounted against applications
consuming decrypted data.
After an encryption key has been provided, fscrypt is not designed to
hide the plaintext file contents or filenames from other users on the
same system, regardless of the visibility of the keyring key.
Instead, existing access control mechanisms such as file mode bits,
POSIX ACLs, LSMs, or mount namespaces should be used for this purpose.
Also note that as long as the encryption keys are *anywhere* in
memory, an online attacker can necessarily compromise them by mounting
a physical attack or by exploiting any kernel security vulnerability
which provides an arbitrary memory read primitive.
While it is ostensibly possible to "evict" keys from the system,
recently accessed encrypted files will remain accessible at least
until the filesystem is unmounted or the VFS caches are dropped, e.g.
using ``echo 2 > /proc/sys/vm/drop_caches``. Even after that, if the
RAM is compromised before being powered off, it will likely still be
possible to recover portions of the plaintext file contents, if not
some of the encryption keys as well. (Since Linux v4.12, all
in-kernel keys related to fscrypt are sanitized before being freed.
However, userspace would need to do its part as well.)
Currently, fscrypt does not prevent a user from maliciously providing
an incorrect key for another user's existing encrypted files. A
protection against this is planned.
Key hierarchy
=============
Master Keys
-----------
Each encrypted directory tree is protected by a *master key*. Master
keys can be up to 64 bytes long, and must be at least as long as the
greater of the key length needed by the contents and filenames
encryption modes being used. For example, if AES-256-XTS is used for
contents encryption, the master key must be 64 bytes (512 bits). Note
that the XTS mode is defined to require a key twice as long as that
required by the underlying block cipher.
To "unlock" an encrypted directory tree, userspace must provide the
appropriate master key. There can be any number of master keys, each
of which protects any number of directory trees on any number of
filesystems.
Userspace should generate master keys either using a cryptographically
secure random number generator, or by using a KDF (Key Derivation
Function). Note that whenever a KDF is used to "stretch" a
lower-entropy secret such as a passphrase, it is critical that a KDF
designed for this purpose be used, such as scrypt, PBKDF2, or Argon2.
Per-file keys
-------------
Master keys are not used to encrypt file contents or names directly.
Instead, a unique key is derived for each encrypted file, including
each regular file, directory, and symbolic link. This has several
advantages:
- In cryptosystems, the same key material should never be used for
different purposes. Using the master key as both an XTS key for
contents encryption and as a CTS-CBC key for filenames encryption
would violate this rule.
- Per-file keys simplify the choice of IVs (Initialization Vectors)
for contents encryption. Without per-file keys, to ensure IV
uniqueness both the inode and logical block number would need to be
encoded in the IVs. This would make it impossible to renumber
inodes, which e.g. ``resize2fs`` can do when resizing an ext4
filesystem. With per-file keys, it is sufficient to encode just the
logical block number in the IVs.
- Per-file keys strengthen the encryption of filenames, where IVs are
reused out of necessity. With a unique key per directory, IV reuse
is limited to within a single directory.
- Per-file keys allow individual files to be securely erased simply by
securely erasing their keys. (Not yet implemented.)
A KDF (Key Derivation Function) is used to derive per-file keys from
the master key. This is done instead of wrapping a randomly-generated
key for each file because it reduces the size of the encryption xattr,
which for some filesystems makes the xattr more likely to fit in-line
in the filesystem's inode table. With a KDF, only a 16-byte nonce is
required --- long enough to make key reuse extremely unlikely. A
wrapped key, on the other hand, would need to be up to 64 bytes ---
the length of an AES-256-XTS key. Furthermore, currently there is no
requirement to support unlocking a file with multiple alternative
master keys or to support rotating master keys. Instead, the master
keys may be wrapped in userspace, e.g. as done by the `fscrypt
<https://github.com/google/fscrypt>`_ tool.
The current KDF encrypts the master key using the 16-byte nonce as an
AES-128-ECB key. The output is used as the derived key. If the
output is longer than needed, then it is truncated to the needed
length. Truncation is the norm for directories and symlinks, since
those use the CTS-CBC encryption mode which requires a key half as
long as that required by the XTS encryption mode.
Note: this KDF meets the primary security requirement, which is to
produce unique derived keys that preserve the entropy of the master
key, assuming that the master key is already a good pseudorandom key.
However, it is nonstandard and has some problems such as being
reversible, so it is generally considered to be a mistake! It may be
replaced with HKDF or another more standard KDF in the future.
Encryption modes and usage
==========================
fscrypt allows one encryption mode to be specified for file contents
and one encryption mode to be specified for filenames. Different
directory trees are permitted to use different encryption modes.
Currently, the following pairs of encryption modes are supported:
- AES-256-XTS for contents and AES-256-CTS-CBC for filenames
- AES-128-CBC for contents and AES-128-CTS-CBC for filenames
- Speck128/256-XTS for contents and Speck128/256-CTS-CBC for filenames
It is strongly recommended to use AES-256-XTS for contents encryption.
AES-128-CBC was added only for low-powered embedded devices with
crypto accelerators such as CAAM or CESA that do not support XTS.
Similarly, Speck128/256 support was only added for older or low-end
CPUs which cannot do AES fast enough -- especially ARM CPUs which have
NEON instructions but not the Cryptography Extensions -- and for which
it would not otherwise be feasible to use encryption at all. It is
not recommended to use Speck on CPUs that have AES instructions.
Speck support is only available if it has been enabled in the crypto
API via CONFIG_CRYPTO_SPECK. Also, on ARM platforms, to get
acceptable performance CONFIG_CRYPTO_SPECK_NEON must be enabled.
New encryption modes can be added relatively easily, without changes
to individual filesystems. However, authenticated encryption (AE)
modes are not currently supported because of the difficulty of dealing
with ciphertext expansion.
For file contents, each filesystem block is encrypted independently.
Currently, only the case where the filesystem block size is equal to
the system's page size (usually 4096 bytes) is supported. With the
XTS mode of operation (recommended), the logical block number within
the file is used as the IV. With the CBC mode of operation (not
recommended), ESSIV is used; specifically, the IV for CBC is the
logical block number encrypted with AES-256, where the AES-256 key is
the SHA-256 hash of the inode's data encryption key.
For filenames, the full filename is encrypted at once. Because of the
requirements to retain support for efficient directory lookups and
filenames of up to 255 bytes, a constant initialization vector (IV) is
used. However, each encrypted directory uses a unique key, which
limits IV reuse to within a single directory. Note that IV reuse in
the context of CTS-CBC encryption means that when the original
filenames share a common prefix at least as long as the cipher block
size (16 bytes for AES), the corresponding encrypted filenames will
also share a common prefix. This is undesirable; it may be fixed in
the future by switching to an encryption mode that is a strong
pseudorandom permutation on arbitrary-length messages, e.g. the HEH
(Hash-Encrypt-Hash) mode.
Since filenames are encrypted with the CTS-CBC mode of operation, the
plaintext and ciphertext filenames need not be multiples of the AES
block size, i.e. 16 bytes. However, the minimum size that can be
encrypted is 16 bytes, so shorter filenames are NUL-padded to 16 bytes
before being encrypted. In addition, to reduce leakage of filename
lengths via their ciphertexts, all filenames are NUL-padded to the
next 4, 8, 16, or 32-byte boundary (configurable). 32 is recommended
since this provides the best confidentiality, at the cost of making
directory entries consume slightly more space. Note that since NUL
(``\0``) is not otherwise a valid character in filenames, the padding
will never produce duplicate plaintexts.
Symbolic link targets are considered a type of filename and are
encrypted in the same way as filenames in directory entries. Each
symlink also uses a unique key; hence, the hardcoded IV is not a
problem for symlinks.
User API
========
Setting an encryption policy
----------------------------
The FS_IOC_SET_ENCRYPTION_POLICY ioctl sets an encryption policy on an
empty directory or verifies that a directory or regular file already
has the specified encryption policy. It takes in a pointer to a
:c:type:`struct fscrypt_policy`, defined as follows::
#define FS_KEY_DESCRIPTOR_SIZE 8
struct fscrypt_policy {
__u8 version;
__u8 contents_encryption_mode;
__u8 filenames_encryption_mode;
__u8 flags;
__u8 master_key_descriptor[FS_KEY_DESCRIPTOR_SIZE];
};
This structure must be initialized as follows:
- ``version`` must be 0.
- ``contents_encryption_mode`` and ``filenames_encryption_mode`` must
be set to constants from ``<linux/fs.h>`` which identify the
encryption modes to use. If unsure, use
FS_ENCRYPTION_MODE_AES_256_XTS (1) for ``contents_encryption_mode``
and FS_ENCRYPTION_MODE_AES_256_CTS (4) for
``filenames_encryption_mode``.
- ``flags`` must be set to a value from ``<linux/fs.h>`` which
identifies the amount of NUL-padding to use when encrypting
filenames. If unsure, use FS_POLICY_FLAGS_PAD_32 (0x3).
- ``master_key_descriptor`` specifies how to find the master key in
the keyring; see `Adding keys`_. It is up to userspace to choose a
unique ``master_key_descriptor`` for each master key. The e4crypt
and fscrypt tools use the first 8 bytes of
``SHA-512(SHA-512(master_key))``, but this particular scheme is not
required. Also, the master key need not be in the keyring yet when
FS_IOC_SET_ENCRYPTION_POLICY is executed. However, it must be added
before any files can be created in the encrypted directory.
If the file is not yet encrypted, then FS_IOC_SET_ENCRYPTION_POLICY
verifies that the file is an empty directory. If so, the specified
encryption policy is assigned to the directory, turning it into an
encrypted directory. After that, and after providing the
corresponding master key as described in `Adding keys`_, all regular
files, directories (recursively), and symlinks created in the
directory will be encrypted, inheriting the same encryption policy.
The filenames in the directory's entries will be encrypted as well.
Alternatively, if the file is already encrypted, then
FS_IOC_SET_ENCRYPTION_POLICY validates that the specified encryption
policy exactly matches the actual one. If they match, then the ioctl
returns 0. Otherwise, it fails with EEXIST. This works on both
regular files and directories, including nonempty directories.
Note that the ext4 filesystem does not allow the root directory to be
encrypted, even if it is empty. Users who want to encrypt an entire
filesystem with one key should consider using dm-crypt instead.
FS_IOC_SET_ENCRYPTION_POLICY can fail with the following errors:
- ``EACCES``: the file is not owned by the process's uid, nor does the
process have the CAP_FOWNER capability in a namespace with the file
owner's uid mapped
- ``EEXIST``: the file is already encrypted with an encryption policy
different from the one specified
- ``EINVAL``: an invalid encryption policy was specified (invalid
version, mode(s), or flags)
- ``ENOTDIR``: the file is unencrypted and is a regular file, not a
directory
- ``ENOTEMPTY``: the file is unencrypted and is a nonempty directory
- ``ENOTTY``: this type of filesystem does not implement encryption
- ``EOPNOTSUPP``: the kernel was not configured with encryption
support for this filesystem, or the filesystem superblock has not
had encryption enabled on it. (For example, to use encryption on an
ext4 filesystem, CONFIG_EXT4_ENCRYPTION must be enabled in the
kernel config, and the superblock must have had the "encrypt"
feature flag enabled using ``tune2fs -O encrypt`` or ``mkfs.ext4 -O
encrypt``.)
- ``EPERM``: this directory may not be encrypted, e.g. because it is
the root directory of an ext4 filesystem
- ``EROFS``: the filesystem is readonly
Getting an encryption policy
----------------------------
The FS_IOC_GET_ENCRYPTION_POLICY ioctl retrieves the :c:type:`struct
fscrypt_policy`, if any, for a directory or regular file. See above
for the struct definition. No additional permissions are required
beyond the ability to open the file.
FS_IOC_GET_ENCRYPTION_POLICY can fail with the following errors:
- ``EINVAL``: the file is encrypted, but it uses an unrecognized
encryption context format
- ``ENODATA``: the file is not encrypted
- ``ENOTTY``: this type of filesystem does not implement encryption
- ``EOPNOTSUPP``: the kernel was not configured with encryption
support for this filesystem
Note: if you only need to know whether a file is encrypted or not, on
most filesystems it is also possible to use the FS_IOC_GETFLAGS ioctl
and check for FS_ENCRYPT_FL, or to use the statx() system call and
check for STATX_ATTR_ENCRYPTED in stx_attributes.
Getting the per-filesystem salt
-------------------------------
Some filesystems, such as ext4 and F2FS, also support the deprecated
ioctl FS_IOC_GET_ENCRYPTION_PWSALT. This ioctl retrieves a randomly
generated 16-byte value stored in the filesystem superblock. This
value is intended to used as a salt when deriving an encryption key
from a passphrase or other low-entropy user credential.
FS_IOC_GET_ENCRYPTION_PWSALT is deprecated. Instead, prefer to
generate and manage any needed salt(s) in userspace.
Adding keys
-----------
To provide a master key, userspace must add it to an appropriate
keyring using the add_key() system call (see:
``Documentation/security/keys/core.rst``). The key type must be
"logon"; keys of this type are kept in kernel memory and cannot be
read back by userspace. The key description must be "fscrypt:"
followed by the 16-character lower case hex representation of the
``master_key_descriptor`` that was set in the encryption policy. The
key payload must conform to the following structure::
#define FS_MAX_KEY_SIZE 64
struct fscrypt_key {
u32 mode;
u8 raw[FS_MAX_KEY_SIZE];
u32 size;
};
``mode`` is ignored; just set it to 0. The actual key is provided in
``raw`` with ``size`` indicating its size in bytes. That is, the
bytes ``raw[0..size-1]`` (inclusive) are the actual key.
The key description prefix "fscrypt:" may alternatively be replaced
with a filesystem-specific prefix such as "ext4:". However, the
filesystem-specific prefixes are deprecated and should not be used in
new programs.
There are several different types of keyrings in which encryption keys
may be placed, such as a session keyring, a user session keyring, or a
user keyring. Each key must be placed in a keyring that is "attached"
to all processes that might need to access files encrypted with it, in
the sense that request_key() will find the key. Generally, if only
processes belonging to a specific user need to access a given
encrypted directory and no session keyring has been installed, then
that directory's key should be placed in that user's user session
keyring or user keyring. Otherwise, a session keyring should be
installed if needed, and the key should be linked into that session
keyring, or in a keyring linked into that session keyring.
Note: introducing the complex visibility semantics of keyrings here
was arguably a mistake --- especially given that by design, after any
process successfully opens an encrypted file (thereby setting up the
per-file key), possessing the keyring key is not actually required for
any process to read/write the file until its in-memory inode is
evicted. In the future there probably should be a way to provide keys
directly to the filesystem instead, which would make the intended
semantics clearer.
Access semantics
================
With the key
------------
With the encryption key, encrypted regular files, directories, and
symlinks behave very similarly to their unencrypted counterparts ---
after all, the encryption is intended to be transparent. However,
astute users may notice some differences in behavior:
- Unencrypted files, or files encrypted with a different encryption
policy (i.e. different key, modes, or flags), cannot be renamed or
linked into an encrypted directory; see `Encryption policy
enforcement`_. Attempts to do so will fail with EPERM. However,
encrypted files can be renamed within an encrypted directory, or
into an unencrypted directory.
- Direct I/O is not supported on encrypted files. Attempts to use
direct I/O on such files will fall back to buffered I/O.
- The fallocate operations FALLOC_FL_COLLAPSE_RANGE,
FALLOC_FL_INSERT_RANGE, and FALLOC_FL_ZERO_RANGE are not supported
on encrypted files and will fail with EOPNOTSUPP.
- Online defragmentation of encrypted files is not supported. The
EXT4_IOC_MOVE_EXT and F2FS_IOC_MOVE_RANGE ioctls will fail with
EOPNOTSUPP.
- The ext4 filesystem does not support data journaling with encrypted
regular files. It will fall back to ordered data mode instead.
- DAX (Direct Access) is not supported on encrypted files.
- The st_size of an encrypted symlink will not necessarily give the
length of the symlink target as required by POSIX. It will actually
give the length of the ciphertext, which will be slightly longer
than the plaintext due to NUL-padding and an extra 2-byte overhead.
- The maximum length of an encrypted symlink is 2 bytes shorter than
the maximum length of an unencrypted symlink. For example, on an
EXT4 filesystem with a 4K block size, unencrypted symlinks can be up
to 4095 bytes long, while encrypted symlinks can only be up to 4093
bytes long (both lengths excluding the terminating null).
Note that mmap *is* supported. This is possible because the pagecache
for an encrypted file contains the plaintext, not the ciphertext.
Without the key
---------------
Some filesystem operations may be performed on encrypted regular
files, directories, and symlinks even before their encryption key has
been provided:
- File metadata may be read, e.g. using stat().
- Directories may be listed, in which case the filenames will be
listed in an encoded form derived from their ciphertext. The
current encoding algorithm is described in `Filename hashing and
encoding`_. The algorithm is subject to change, but it is
guaranteed that the presented filenames will be no longer than
NAME_MAX bytes, will not contain the ``/`` or ``\0`` characters, and
will uniquely identify directory entries.
The ``.`` and ``..`` directory entries are special. They are always
present and are not encrypted or encoded.
- Files may be deleted. That is, nondirectory files may be deleted
with unlink() as usual, and empty directories may be deleted with
rmdir() as usual. Therefore, ``rm`` and ``rm -r`` will work as
expected.
- Symlink targets may be read and followed, but they will be presented
in encrypted form, similar to filenames in directories. Hence, they
are unlikely to point to anywhere useful.
Without the key, regular files cannot be opened or truncated.
Attempts to do so will fail with ENOKEY. This implies that any
regular file operations that require a file descriptor, such as
read(), write(), mmap(), fallocate(), and ioctl(), are also forbidden.
Also without the key, files of any type (including directories) cannot
be created or linked into an encrypted directory, nor can a name in an
encrypted directory be the source or target of a rename, nor can an
O_TMPFILE temporary file be created in an encrypted directory. All
such operations will fail with ENOKEY.
It is not currently possible to backup and restore encrypted files
without the encryption key. This would require special APIs which
have not yet been implemented.
Encryption policy enforcement
=============================
After an encryption policy has been set on a directory, all regular
files, directories, and symbolic links created in that directory
(recursively) will inherit that encryption policy. Special files ---
that is, named pipes, device nodes, and UNIX domain sockets --- will
not be encrypted.
Except for those special files, it is forbidden to have unencrypted
files, or files encrypted with a different encryption policy, in an
encrypted directory tree. Attempts to link or rename such a file into
an encrypted directory will fail with EPERM. This is also enforced
during ->lookup() to provide limited protection against offline
attacks that try to disable or downgrade encryption in known locations
where applications may later write sensitive data. It is recommended
that systems implementing a form of "verified boot" take advantage of
this by validating all top-level encryption policies prior to access.
Implementation details
======================
Encryption context
------------------
An encryption policy is represented on-disk by a :c:type:`struct
fscrypt_context`. It is up to individual filesystems to decide where
to store it, but normally it would be stored in a hidden extended
attribute. It should *not* be exposed by the xattr-related system
calls such as getxattr() and setxattr() because of the special
semantics of the encryption xattr. (In particular, there would be
much confusion if an encryption policy were to be added to or removed
from anything other than an empty directory.) The struct is defined
as follows::
#define FS_KEY_DESCRIPTOR_SIZE 8
#define FS_KEY_DERIVATION_NONCE_SIZE 16
struct fscrypt_context {
u8 format;
u8 contents_encryption_mode;
u8 filenames_encryption_mode;
u8 flags;
u8 master_key_descriptor[FS_KEY_DESCRIPTOR_SIZE];
u8 nonce[FS_KEY_DERIVATION_NONCE_SIZE];
};
Note that :c:type:`struct fscrypt_context` contains the same
information as :c:type:`struct fscrypt_policy` (see `Setting an
encryption policy`_), except that :c:type:`struct fscrypt_context`
also contains a nonce. The nonce is randomly generated by the kernel
and is used to derive the inode's encryption key as described in
`Per-file keys`_.
Data path changes
-----------------
For the read path (->readpage()) of regular files, filesystems can
read the ciphertext into the page cache and decrypt it in-place. The
page lock must be held until decryption has finished, to prevent the
page from becoming visible to userspace prematurely.
For the write path (->writepage()) of regular files, filesystems
cannot encrypt data in-place in the page cache, since the cached
plaintext must be preserved. Instead, filesystems must encrypt into a
temporary buffer or "bounce page", then write out the temporary
buffer. Some filesystems, such as UBIFS, already use temporary
buffers regardless of encryption. Other filesystems, such as ext4 and
F2FS, have to allocate bounce pages specially for encryption.
Filename hashing and encoding
-----------------------------
Modern filesystems accelerate directory lookups by using indexed
directories. An indexed directory is organized as a tree keyed by
filename hashes. When a ->lookup() is requested, the filesystem
normally hashes the filename being looked up so that it can quickly
find the corresponding directory entry, if any.
With encryption, lookups must be supported and efficient both with and
without the encryption key. Clearly, it would not work to hash the
plaintext filenames, since the plaintext filenames are unavailable
without the key. (Hashing the plaintext filenames would also make it
impossible for the filesystem's fsck tool to optimize encrypted
directories.) Instead, filesystems hash the ciphertext filenames,
i.e. the bytes actually stored on-disk in the directory entries. When
asked to do a ->lookup() with the key, the filesystem just encrypts
the user-supplied name to get the ciphertext.
Lookups without the key are more complicated. The raw ciphertext may
contain the ``\0`` and ``/`` characters, which are illegal in
filenames. Therefore, readdir() must base64-encode the ciphertext for
presentation. For most filenames, this works fine; on ->lookup(), the
filesystem just base64-decodes the user-supplied name to get back to
the raw ciphertext.
However, for very long filenames, base64 encoding would cause the
filename length to exceed NAME_MAX. To prevent this, readdir()
actually presents long filenames in an abbreviated form which encodes
a strong "hash" of the ciphertext filename, along with the optional
filesystem-specific hash(es) needed for directory lookups. This
allows the filesystem to still, with a high degree of confidence, map
the filename given in ->lookup() back to a particular directory entry
that was previously listed by readdir(). See :c:type:`struct
fscrypt_digested_name` in the source for more details.
Note that the precise way that filenames are presented to userspace
without the key is subject to change in the future. It is only meant
as a way to temporarily present valid filenames so that commands like
``rm -r`` work as expected on encrypted directories.

12
Documentation/networking/ip-sysctl.txt
View file

@ -745,6 +745,18 @@ tcp_challenge_ack_limit - INTEGER
in RFC 5961 (Improving TCP's Robustness to Blind In-Window Attacks)
Default: 100
MPTCP variables:
mptcp_enabled - INTEGER
Enable or disable Multipath TCP for new connections.
Possible values are:
0: Multipath TCP is disabled on all TCP-sockets that are newly created.
1: Multipath TCP is enabled by default on all new TCP-sockets. Note that
existing sockets in LISTEN-state will still use regular TCP.
2: Enables Multipath TCP only upon the request of the application
through the socket-option MPTCP_ENABLED.
UDP variables:
udp_mem - vector of 3 INTEGERs: min, pressure, max

2
Documentation/zh_CN/HOWTO
View file

@ -1,4 +1,4 @@
Chinese translated version of Documentation/HOWTO
Chinese translated version of Documentation/HOWTO
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem

2
Documentation/zh_CN/SubmittingDrivers
View file

@ -1,4 +1,4 @@
Chinese translated version of Documentation/SubmittingDrivers
Chinese translated version of Documentation/SubmittingDrivers
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem

2
Documentation/zh_CN/email-clients.txt
View file

@ -1,4 +1,4 @@
Chinese translated version of Documentation/email-clients.txt
Chinese translated version of Documentation/email-clients.txt
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem

2
Documentation/zh_CN/sparse.txt
View file

@ -1,4 +1,4 @@
Chinese translated version of Documentation/sparse.txt
Chinese translated version of Documentation/sparse.txt
If you have any comment or update to the content, please contact the
original document maintainer directly. However, if you have a problem

8
Kconfig
View file

@ -8,4 +8,12 @@ config SRCARCH
string
option env="SRCARCH"
config ANDROID_VERSION
string
option env="ANDROID_VERSION"
config ANDROID_MAJOR_VERSION
string
option env="ANDROID_MAJOR_VERSION"
source "arch/$SRCARCH/Kconfig"

46
Makefile
View file

@ -254,8 +254,11 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/x86/ -e s/x86_64/x86/ \
# "make" in the configured kernel build directory always uses that.
# Default value for CROSS_COMPILE is not to prefix executables
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
ARCH ?= $(SUBARCH)
CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
#ARCH ?= $(SUBARCH)
#CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%)
ARCH ?= arm64
#CROSS_COMPILE ?= ../PLATFORM/prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin/aarch64-linux-android-
CROSS_COMPILE ?= $(srctree)/toolchain/gcc-cfp/gcc-ibv-jopp/aarch64-linux-android-4.9/bin/aarch64-linux-android-
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)
@ -398,6 +401,7 @@ KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -fno-common \
-Werror-implicit-function-declaration \
-Wno-format-security \
-Werror \
-std=gnu89
KBUILD_CPPFLAGS := -D__KERNEL__
KBUILD_AFLAGS_KERNEL :=
@ -468,6 +472,26 @@ asm-generic:
$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.asm-generic \
src=uapi/asm obj=arch/$(SRCARCH)/include/generated/uapi/asm
ifneq ($(PLATFORM_VERSION), )
PLATFORM_VERSION_NUMBER=$(shell $(CONFIG_SHELL) $(srctree)/scripts/android-version.sh $(PLATFORM_VERSION))
MAJOR_VERSION=$(shell $(CONFIG_SHELL) $(srctree)/scripts/android-major-version.sh $(PLATFORM_VERSION))
export ANDROID_VERSION=$(PLATFORM_VERSION_NUMBER)
export ANDROID_MAJOR_VERSION=$(MAJOR_VERSION)
KBUILD_CFLAGS += -DANDROID_VERSION=$(PLATFORM_VERSION_NUMBER)
KBUILD_CFLAGS += -DANDROID_MAJOR_VERSION=$(MAJOR_VERSION)
# Example
#SELINUX_DIR=$(shell $(CONFIG_SHELL) $(srctree)/scripts/find_matching_major.sh "$(srctree)" "security/selinux" "$(ANDROID_MAJOR_VERSION)")
else
export ANDROID_VERSION=990000
KBUILD_CFLAGS += -DANDROID_VERSION=990000
endif
PHONY += replace_dirs
replace_dirs:
ifneq ($(PLATFORM_VERSION), )
# Example
@echo "skip replace selinux"
#$(Q)$(CONFIG_SHELL) $(srctree)/scripts/replace_dir.sh "$(srctree)" "security/selinux" "$(SELINUX_DIR)"
endif
# To make sure we do not include .config for any of the *config targets
# catch them early, and hand them over to scripts/kconfig/Makefile
# It is allowed to specify more targets when calling make, including
@ -537,10 +561,10 @@ ifeq ($(config-targets),1)
include arch/$(SRCARCH)/Makefile
export KBUILD_DEFCONFIG KBUILD_KCONFIG
config: scripts_basic outputmakefile FORCE
config: scripts_basic outputmakefile replace_dirs FORCE
$(Q)$(MAKE) $(build)=scripts/kconfig $@
%config: scripts_basic outputmakefile FORCE
%config: scripts_basic outputmakefile replace_dirs FORCE
$(Q)$(MAKE) $(build)=scripts/kconfig $@
else
@ -826,6 +850,12 @@ ifdef CONFIG_DEBUG_INFO_DWARF4
KBUILD_CFLAGS += $(call cc-option, -gdwarf-4,)
endif
ifdef CONFIG_RKP_CFP_JOPP
# Don't use jump tables for switch statements, since this generates indirect jump (br)
# instructions, which are very dangerous for kernel control flow integrity.
KBUILD_CFLAGS += -fno-jump-tables
endif
ifdef CONFIG_DEBUG_INFO_REDUCED
KBUILD_CFLAGS += $(call cc-option, -femit-struct-debug-baseonly) \
$(call cc-option,-fno-var-tracking)
@ -921,6 +951,14 @@ ifeq ($(CONFIG_STRIP_ASM_SYMS),y)
LDFLAGS_vmlinux += $(call ld-option, -X,)
endif
ifneq ($(SEC_BUILD_CONF_USE_FINGERPRINT_TZ), false)
ifeq ($(CONFIG_SENSORS_FINGERPRINT), y)
ifneq ($(CONFIG_SEC_FACTORY), y)
export KBUILD_FP_SENSOR_CFLAGS := -DENABLE_SENSORS_FPRINT_SECURE
endif
endif
endif
# Default kernel image to build when no specific target is given.
# KBUILD_IMAGE may be overruled on the command line or
# set in the environment

2
arch/arc/Kconfig
View file

@ -105,7 +105,7 @@ endmenu
choice
prompt "ARC Instruction Set"
default ISA_ARCOMPACT
default ISA_ARCV2
config ISA_ARCOMPACT
bool "ARCompact ISA"

41
arch/arc/Makefile
View file

@ -8,34 +8,12 @@
UTS_MACHINE := arc
ifeq ($(CROSS_COMPILE),)
ifndef CONFIG_CPU_BIG_ENDIAN
CROSS_COMPILE := arc-linux-
else
CROSS_COMPILE := arceb-linux-
endif
endif
KBUILD_DEFCONFIG := nsim_hs_defconfig
KBUILD_DEFCONFIG := nsim_700_defconfig
cflags-y += -fno-common -pipe -fno-builtin -D__linux__
cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__
cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7
cflags-$(CONFIG_ISA_ARCV2) += -mcpu=archs
is_700 = $(shell $(CC) -dM -E - < /dev/null | grep -q "ARC700" && echo 1 || echo 0)
ifdef CONFIG_ISA_ARCOMPACT
ifeq ($(is_700), 0)
$(error Toolchain not configured for ARCompact builds)
endif
endif
ifdef CONFIG_ISA_ARCV2
ifeq ($(is_700), 1)
$(error Toolchain not configured for ARCv2 builds)
endif
endif
ifdef CONFIG_ARC_CURR_IN_REG
# For a global register defintion, make sure it gets passed to every file
# We had a customer reported bug where some code built in kernel was NOT using
@ -89,7 +67,7 @@ ldflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
# --build-id w/o "-marclinux". Default arc-elf32-ld is OK
ldflags-$(upto_gcc44) += -marclinux
LIBGCC := $(shell $(CC) $(cflags-y) --print-libgcc-file-name)
LIBGCC = $(shell $(CC) $(cflags-y) --print-libgcc-file-name)
# Modules with short calls might break for calls into builtin-kernel
KBUILD_CFLAGS_MODULE += -mlong-calls -mno-millicode
@ -141,16 +119,3 @@ dtbs: scripts
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
# Hacks to enable final link due to absence of link-time branch relexation
# and gcc choosing optimal(shorter) branches at -O3
#
# vineetg Feb 2010: -mlong-calls switched off for overall kernel build
# However lib/decompress_inflate.o (.init.text) calls
# zlib_inflate_workspacesize (.text) causing relocation errors.
# Thus forcing all exten calls in this file to be long calls
export CFLAGS_decompress_inflate.o = -mmedium-calls
export CFLAGS_initramfs.o = -mmedium-calls
ifdef CONFIG_SMP
export CFLAGS_core.o = -mmedium-calls
endif

1
arch/arc/configs/axs101_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y

1
arch/arc/configs/nps_defconfig
View file

@ -15,6 +15,7 @@ CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y

1
arch/arc/configs/nsim_700_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_LBDAF is not set

1
arch/arc/configs/nsimosci_defconfig
View file

@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_LBDAF is not set

1
arch/arc/configs/tb10x_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_KALLSYMS_ALL=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y

1
arch/arc/configs/zebu_hs_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set

1
arch/arc/configs/zebu_hs_smp_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set

3
arch/arm/common/Kconfig
View file

@ -18,6 +18,3 @@ config SHARP_PARAM
config SHARP_SCOOP
bool
config FIQ_GLUE
bool
select FIQ

1
arch/arm/common/Makefile
View file

@ -4,7 +4,6 @@
obj-y += firmware.o
obj-$(CONFIG_FIQ_GLUE) += fiq_glue.o fiq_glue_setup.o
obj-$(CONFIG_ICST) += icst.o
obj-$(CONFIG_SA1111) += sa1111.o
obj-$(CONFIG_DMABOUNCE) += dmabounce.o

118
arch/arm/common/fiq_glue.S
View file

@ -1,118 +0,0 @@
/*
* Copyright (C) 2008 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
.global fiq_glue_end
/* fiq stack: r0-r15,cpsr,spsr of interrupted mode */
ENTRY(fiq_glue)
/* store pc, cpsr from previous mode, reserve space for spsr */
mrs r12, spsr
sub lr, lr, #4
subs r10, #1
bne nested_fiq
str r12, [sp, #-8]!
str lr, [sp, #-4]!
/* store r8-r14 from previous mode */
sub sp, sp, #(7 * 4)
stmia sp, {r8-r14}^
nop
/* store r0-r7 from previous mode */
stmfd sp!, {r0-r7}
/* setup func(data,regs) arguments */
mov r0, r9
mov r1, sp
mov r3, r8
mov r7, sp
/* Get sp and lr from non-user modes */
and r4, r12, #MODE_MASK
cmp r4, #USR_MODE
beq fiq_from_usr_mode
mov r7, sp
orr r4, r4, #(PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r4
str sp, [r7, #(4 * 13)]
str lr, [r7, #(4 * 14)]
mrs r5, spsr
str r5, [r7, #(4 * 17)]
cmp r4, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
/* use fiq stack if we reenter this mode */
subne sp, r7, #(4 * 3)
fiq_from_usr_mode:
msr cpsr_c, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
mov r2, sp
sub sp, r7, #12
stmfd sp!, {r2, ip, lr}
/* call func(data,regs) */
blx r3
ldmfd sp, {r2, ip, lr}
mov sp, r2
/* restore/discard saved state */
cmp r4, #USR_MODE
beq fiq_from_usr_mode_exit
msr cpsr_c, r4
ldr sp, [r7, #(4 * 13)]
ldr lr, [r7, #(4 * 14)]
msr spsr_cxsf, r5
fiq_from_usr_mode_exit:
msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT)
ldmfd sp!, {r0-r7}
ldr lr, [sp, #(4 * 7)]
ldr r12, [sp, #(4 * 8)]
add sp, sp, #(10 * 4)
exit_fiq:
msr spsr_cxsf, r12
add r10, #1
cmp r11, #0
moveqs pc, lr
bx r11 /* jump to custom fiq return function */
nested_fiq:
orr r12, r12, #(PSR_F_BIT)
b exit_fiq
fiq_glue_end:
ENTRY(fiq_glue_setup) /* func, data, sp, smc call number */
stmfd sp!, {r4}
mrs r4, cpsr
msr cpsr_c, #(FIQ_MODE | PSR_I_BIT | PSR_F_BIT)
movs r8, r0
mov r9, r1
mov sp, r2
mov r11, r3
moveq r10, #0
movne r10, #1
msr cpsr_c, r4
ldmfd sp!, {r4}
bx lr

147
arch/arm/common/fiq_glue_setup.c
View file

@ -1,147 +0,0 @@
/*
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/slab.h>
#include <asm/fiq.h>
#include <asm/fiq_glue.h>
extern unsigned char fiq_glue, fiq_glue_end;
extern void fiq_glue_setup(void *func, void *data, void *sp,
fiq_return_handler_t fiq_return_handler);
static struct fiq_handler fiq_debbuger_fiq_handler = {
.name = "fiq_glue",
};
DEFINE_PER_CPU(void *, fiq_stack);
static struct fiq_glue_handler *current_handler;
static fiq_return_handler_t fiq_return_handler;
static DEFINE_MUTEX(fiq_glue_lock);
static void fiq_glue_setup_helper(void *info)
{
struct fiq_glue_handler *handler = info;
fiq_glue_setup(handler->fiq, handler,
__get_cpu_var(fiq_stack) + THREAD_START_SP,
fiq_return_handler);
}
int fiq_glue_register_handler(struct fiq_glue_handler *handler)
{
int ret;
int cpu;
if (!handler || !handler->fiq)
return -EINVAL;
mutex_lock(&fiq_glue_lock);
if (fiq_stack) {
ret = -EBUSY;
goto err_busy;
}
for_each_possible_cpu(cpu) {
void *stack;
stack = (void *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
if (WARN_ON(!stack)) {
ret = -ENOMEM;
goto err_alloc_fiq_stack;
}
per_cpu(fiq_stack, cpu) = stack;
}
ret = claim_fiq(&fiq_debbuger_fiq_handler);
if (WARN_ON(ret))
goto err_claim_fiq;
current_handler = handler;
on_each_cpu(fiq_glue_setup_helper, handler, true);
set_fiq_handler(&fiq_glue, &fiq_glue_end - &fiq_glue);
mutex_unlock(&fiq_glue_lock);
return 0;
err_claim_fiq:
err_alloc_fiq_stack:
for_each_possible_cpu(cpu) {
__free_pages(per_cpu(fiq_stack, cpu), THREAD_SIZE_ORDER);
per_cpu(fiq_stack, cpu) = NULL;
}
err_busy:
mutex_unlock(&fiq_glue_lock);
return ret;
}
static void fiq_glue_update_return_handler(void (*fiq_return)(void))
{
fiq_return_handler = fiq_return;
if (current_handler)
on_each_cpu(fiq_glue_setup_helper, current_handler, true);
}
int fiq_glue_set_return_handler(void (*fiq_return)(void))
{
int ret;
mutex_lock(&fiq_glue_lock);
if (fiq_return_handler) {
ret = -EBUSY;
goto err_busy;
}
fiq_glue_update_return_handler(fiq_return);
ret = 0;
err_busy:
mutex_unlock(&fiq_glue_lock);
return ret;
}
EXPORT_SYMBOL(fiq_glue_set_return_handler);
int fiq_glue_clear_return_handler(void (*fiq_return)(void))
{
int ret;
mutex_lock(&fiq_glue_lock);
if (WARN_ON(fiq_return_handler != fiq_return)) {
ret = -EINVAL;
goto err_inval;
}
fiq_glue_update_return_handler(NULL);
ret = 0;
err_inval:
mutex_unlock(&fiq_glue_lock);
return ret;
}
EXPORT_SYMBOL(fiq_glue_clear_return_handler);
/**
* fiq_glue_resume - Restore fiqs after suspend or low power idle states
*
* This must be called before calling local_fiq_enable after returning from a
* power state where the fiq mode registers were lost. If a driver provided
* a resume hook when it registered the handler it will be called.
*/
void fiq_glue_resume(void)
{
if (!current_handler)
return;
fiq_glue_setup(current_handler->fiq, current_handler,
__get_cpu_var(fiq_stack) + THREAD_START_SP,
fiq_return_handler);
if (current_handler->resume)
current_handler->resume(current_handler);
}

1
arch/arm/include/asm/thread_info.h
View file

@ -148,6 +148,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
#define TIF_USING_IWMMXT 17
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 20
#define TIF_MEMALLOC 29 /* allocating pages now */
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)

2
arch/arm/kernel/setup.c
View file

@ -1088,7 +1088,9 @@ void __init setup_arch(char **cmdline_p)
parse_early_param();
#ifdef CONFIG_MMU
set_memsize_kernel_type(MEMSIZE_KERNEL_PAGING);
early_paging_init(mdesc);
set_memsize_kernel_type(MEMSIZE_KERNEL_OTHERS);
#endif
setup_dma_zone(mdesc);
xen_early_init();

15
arch/arm/mm/init.c
View file

@ -230,11 +230,15 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
void __init arm_memblock_init(const struct machine_desc *mdesc)
{
/* Register the kernel text, kernel data and initrd with memblock. */
set_memsize_kernel_type(MEMSIZE_KERNEL_KERNEL);
#ifdef CONFIG_XIP_KERNEL
memblock_reserve(__pa(_sdata), _end - _sdata);
#else
memblock_reserve(__pa(_stext), _end - _stext);
#endif
set_memsize_kernel_type(MEMSIZE_KERNEL_STOP);
record_memsize_reserved("initmem", __pa(__init_begin),
__init_end - __init_begin, false, false);
#ifdef CONFIG_BLK_DEV_INITRD
/* FDT scan will populate initrd_start */
if (initrd_start && !phys_initrd_size) {
@ -255,7 +259,13 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
phys_initrd_start = phys_initrd_size = 0;
}
if (phys_initrd_size) {
phys_addr_t start_down, end_up;
memblock_reserve(phys_initrd_start, phys_initrd_size);
start_down = phys_initrd_start & PAGE_MASK;
end_up = PAGE_ALIGN(phys_initrd_start + phys_initrd_size);
record_memsize_reserved("initrd", start_down, end_up - start_down,
false, false);
/* Now convert initrd to virtual addresses */
initrd_start = __phys_to_virt(phys_initrd_start);
@ -263,6 +273,7 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
}
#endif
set_memsize_kernel_type(MEMSIZE_KERNEL_OTHERS);
arm_mm_memblock_reserve();
/* reserve any platform specific memblock areas */
@ -270,10 +281,12 @@ void __init arm_memblock_init(const struct machine_desc *mdesc)
mdesc->reserve();
early_init_fdt_reserve_self();
set_memsize_kernel_type(MEMSIZE_KERNEL_STOP);
early_init_fdt_scan_reserved_mem();
/* reserve memory for DMA contiguous allocations */
dma_contiguous_reserve(arm_dma_limit);
set_memsize_kernel_type(MEMSIZE_KERNEL_OTHERS);
arm_memblock_steal_permitted = false;
memblock_dump_all();
@ -365,6 +378,7 @@ static void __init free_unused_memmap(void)
unsigned long start, prev_end = 0;
struct memblock_region *reg;
set_memsize_kernel_type(MEMSIZE_KERNEL_PAGING);
/*
* This relies on each bank being in address order.
* The banks are sorted previously in bootmem_init().
@ -408,6 +422,7 @@ static void __init free_unused_memmap(void)
free_memmap(prev_end,
ALIGN(prev_end, PAGES_PER_SECTION));
#endif
set_memsize_kernel_type(MEMSIZE_KERNEL_MM_INIT);
}
#ifdef CONFIG_HIGHMEM

2
arch/arm/mm/mmu.c
View file

@ -1620,6 +1620,7 @@ void __init paging_init(const struct machine_desc *mdesc)
{
void *zero_page;
set_memsize_kernel_type(MEMSIZE_KERNEL_PAGING);
build_mem_type_table();
prepare_page_table();
map_lowmem();
@ -1639,4 +1640,5 @@ void __init paging_init(const struct machine_desc *mdesc)
empty_zero_page = virt_to_page(zero_page);
__flush_dcache_page(NULL, empty_zero_page);
set_memsize_kernel_type(MEMSIZE_KERNEL_OTHERS);
}

245
arch/arm64/Kconfig
View file

@ -26,7 +26,7 @@ config ARM64
select ARM_GIC
select AUDIT_ARCH_COMPAT_GENERIC
select ARM_GIC_V2M if PCI
select ARM_GIC_V3
select ARM_GIC_V3 if !ARCH_EXYNOS
select ARM_GIC_V3_ITS if PCI
select ARM_PSCI_FW
select BUILDTIME_EXTABLE_SORT
@ -110,6 +110,7 @@ config ARM64
select POWER_SUPPLY
select SPARSE_IRQ
select SYSCTL_EXCEPTION_TRACE
select SECCOMP
select THREAD_INFO_IN_TASK
help
ARM 64-bit (AArch64) Linux support.
@ -202,7 +203,7 @@ config GENERIC_CALIBRATE_DELAY
def_bool y
config ZONE_DMA
def_bool y
def_bool n
config HAVE_GENERIC_RCU_GUP
def_bool y
@ -429,6 +430,10 @@ config ARM64_ERRATUM_843419
If unsure, say Y.
config ARM64_ERRATUM_814818
bool "Ananke : Allocating streaming write might deadlock"
default y
config ARM64_ERRATUM_1024718
bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
default y
@ -589,6 +594,113 @@ config SCHED_SMT
MultiThreading at a cost of slightly increased overhead in some
places. If unsure say N here.
config DISABLE_CPU_SCHED_DOMAIN_BALANCE
bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
help
Disables scheduler load-balancing at CPU sched domain level.
config SCHED_HMP
bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
help
Experimental scheduler optimizations for heterogeneous platforms.
Attempts to introspectively select task affinity to optimize power
and performance. Basic support for multiple (>2) cpu types is in place,
but it has only been tested with two types of cpus.
There is currently no support for migration of task groups, hence
!SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
config SCHED_HMP_PRIO_FILTER
bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
depends on SCHED_HMP
help
Enables task priority based HMP migration filter. Any task with
a NICE value above the threshold will always be on low-power cpus
with less compute capacity.
config SCHED_HMP_PRIO_FILTER_VAL
int "NICE priority threshold"
default 5
depends on SCHED_HMP_PRIO_FILTER
config HMP_FAST_CPU_MASK
string "HMP scheduler fast CPU mask"
depends on SCHED_HMP
help
Leave empty to use device tree information.
Specify the cpuids of the fast CPUs in the system as a list string,
e.g. cpuid 0+1 should be specified as 0-1.
config HMP_SLOW_CPU_MASK
string "HMP scheduler slow CPU mask"
depends on SCHED_HMP
help
Leave empty to use device tree information.
Specify the cpuids of the slow CPUs in the system as a list string,
e.g. cpuid 0+1 should be specified as 0-1.
config HMP_VARIABLE_SCALE
bool "Allows changing the load tracking scale through sysfs"
depends on SCHED_HMP
default y
help
When turned on, this option exports the thresholds and load average
period value for the load tracking patches through sysfs.
The values can be modified to change the rate of load accumulation
and the thresholds used for HMP migration.
The load_avg_period_ms is the time in ms to reach a load average of
0.5 for an idle task of 0 load average ratio that start a busy loop.
The up_threshold and down_threshold is the value to go to a faster
CPU or to go back to a slower cpu.
The {up,down}_threshold are devided by 1024 before being compared
to the load average.
For examples, with load_avg_period_ms = 128 and up_threshold = 512,
a running task with a load of 0 will be migrated to a bigger CPU after
128ms, because after 128ms its load_avg_ratio is 0.5 and the real
up_threshold is 0.5.
This patch has the same behavior as changing the Y of the load
average computation to
(1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
but it remove intermadiate overflows in computation.
config HMP_FREQUENCY_INVARIANT_SCALE
bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
depends on HMP_VARIABLE_SCALE && CPU_FREQ
default n
help
Scales the current load contribution in line with the frequency
of the CPU that the task was executed on.
In this version, we use a simple linear scale derived from the
maximum frequency reported by CPUFreq.
Restricting tracked load to be scaled by the CPU's frequency
represents the consumption of possible compute capacity
(rather than consumption of actual instantaneous capacity as
normal) and allows the HMP migration's simple threshold
migration strategy to interact more predictably with CPUFreq's
asynchronous compute capacity changes.
config SCHED_HMP_LITTLE_PACKING
bool "Small task packing for HMP"
depends on SCHED_HMP
default n
help
Allows the HMP Scheduler to pack small tasks into CPUs in the
smallest HMP domain.
Controlled by two sysfs files in sys/kernel/hmp.
packing_enable: 1 to enable, 0 to disable packing. Default 1.
packing_limit: runqueue load ratio where a RQ is considered
to be full. Default is NICE_0_LOAD * 9/8.
config SCHED_HMP_TASK_BASED_SOFTLANDING
bool "(EXPERIMENTAL) Task based softlanding for HMP down migration"
depends on SCHED_HMP && CPU_FREQ
help
Enables task based softlanding when HMP down migration.
The task based softlanding guarantees proper performance
to the down-migrated task by frequency qos lock.
config NR_CPUS
int "Maximum number of CPUs (2-4096)"
range 2 4096
@ -862,6 +974,19 @@ config ARM64_SW_TTBR0_PAN
zeroed area and reserved ASID. The user access routines
restore the valid TTBR0_EL1 temporarily.
menu "JOP Attack Prevention"
config RKP_CFP_JOPP
bool "Function pointer jumps to function entries only."
default n
config RKP_CFP_JOPP_MAGIC
hex
depends on RKP_CFP_JOPP
default "0x00be7bad"
endmenu
menu "ARMv8.1 architectural features"
config ARM64_HW_AFDBM
@ -955,6 +1080,13 @@ config ARM64_MODULE_PLTS
select ARM64_MODULE_CMODEL_LARGE
select HAVE_MOD_ARCH_SPECIFIC
config RELOCATABLE_KERNEL
bool "set kernel to relocatable in both virtual and physical address"
default n
help
This configuare will allow you to config the kernel into position
independent kernel, with '--PIE' insert into LD script.
config RELOCATABLE
bool
help
@ -1106,6 +1238,115 @@ config BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME
default "Image.gz-dtb" if IMG_GZ_DTB
default "Image-dtb" if IMG_DTB
config LOD_SEC
bool "kernel security re-enforcement for Linux On Dex, including cap re-check and seccomp report"
default n
config TIMA
bool "Enable TIMA(Trustzone based Integrity Measurement Archtecture) feature"
default n
config TIMA_LKMAUTH
bool "Enable LKM authentication by TIMA"
depends on MODULES
help
TIMA authenticates loaded kernel modules. Disable it if you don't
want TIMA enabled.
config TIMA_LKM_BLOCK
bool "Block LKM by TIMA"
help
LKM is disapproved by Samsung security policy.
config TIMA_LKMAUTH_CODE_PROT
bool "Support kernel Module"
depends on MODULES
default n
help
When enabled, this feature will mark all Executable sections in an
LKM as RO
config UH
bool "Enable micro hypervisor feature"
depends on !SEC_FACTORY
default n
help
It enables a micro hypervisor.
It's samsung's hypervisor.
RKP and etc can be loaded on it.
please check a memory map for it.
config UH_DEBUG
bool "Enable micro hypervisor debug feature"
depends on UH
default n
help
It's for debugging uH.
config UH_RKP
bool "Enable RKP (Realtime Kernel Protection) UH feature"
depends on UH
default n
help
it protects a kernel text and etc.
config UH_RKP_8G
bool "Support 8G Model"
depends on UH_RKP
default n
help
support 8G
config UH_INFORM
bool "Debugfs for information of the security feature's active/inactive statue"
default n
help
This config has the information of RKP,JOPP,ROPP,KDP,DMV.
It informs that the above feature are whether active or inactive.
config UH_RKP_FIMC_TYPE
bool "Select FIMC type"
depends on UH_RKP
default n
help
it protects a kernel text and etc.
config RKP_KDP
bool "Protection for cred structure"
depends on UH_RKP
depends on !SEC_VTS_TEST
default n
help
Prevents unauthorized cred modification.
config RKP_NS_PROT
bool "Protection for namespace structure"
depends on RKP_KDP
default n
help
Prevents unauthorized namespace modification.
config RKP_DMAP_PROT
bool "Page Double Mapping protection"
depends on RKP_KDP
default n
help
Prevents unauthorized mapping for page table.
config RKP_TEST
bool "Enables rkp test"
depends on UH_RKP && !SAMSUNG_PRODUCT_SHIP
default n
help
it enables rkp test.
config KDP_TEST
bool "Enable KDP test"
depends on RKP_KDP && RKP_NS_PROT && !SAMSUNG_PRODUCT_SHIP
default n
help
enable KDP test.
config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
string "Default dtb names"
depends on BUILD_ARM64_APPENDED_DTB_IMAGE

42
arch/arm64/Kconfig.debug
View file

@ -38,6 +38,14 @@ config ARM64_RANDOMIZE_TEXT_OFFSET
of TEXT_OFFSET and platforms must not require a specific
value.
config DEBUG_EXCEPTION_STACK
bool "Preserve stack data when the exception happened"
default n
help
If this is set, kernel can preserve the specific size of stack data
when an exception occurs from EL1. This can help to fiqure out the
stack data before the exception happened.
config DEBUG_SET_MODULE_RONX
bool "Set loadable kernel module data as NX and text as RO"
depends on MODULES
@ -62,6 +70,40 @@ config DEBUG_ALIGN_RODATA
If in doubt, say N.
comment "Samsung Rooting Restriction Feature"
config SEC_RESTRICT_ROOTING
bool "Samsung Rooting Restriction Feature"
depends on SAMSUNG_PRODUCT_SHIP
default n
help
Restrict unauthorized executions with root permission.
config SEC_RESTRICT_SETUID
bool "Restrict changing root privilege except allowed process"
depends on SEC_RESTRICT_ROOTING
default y
help
Say Y here if you want to restrict functions related setuid. Only allowed
process can chanage ROOT privilege. Saying N will not restrict changing
permission.
config SEC_RESTRICT_FORK
bool "Restrict forking process except allowed process"
depends on SEC_RESTRICT_ROOTING
default y
help
Say Y here if you want to restrict function related fork. Process matched
special condition will be not forked. Saying N will not restrict forking
process.
config SEC_RESTRICT_ROOTING_LOG
bool "Print restricted result to kernel log"
depends on SEC_RESTRICT_ROOTING
default n
help
Say Y here if you want to see result of restricting SETUID or FORK. It will
be displayed by kernel error log. Saying N will not be displayed anything.
source "drivers/hwtracing/coresight/Kconfig"
endmenu

70
arch/arm64/Kconfig.platforms
View file

@ -230,4 +230,74 @@ config ARCH_ZYNQMP
help
This enables support for Xilinx ZynqMP Family
menu "Samsung Exynos"
config ARCH_EXYNOS
bool
config SOC_EXYNOS8895
bool "Samsung EXYNOS8895"
select SOC_SAMSUNG
select ARCH_EXYNOS
select ARCH_HAS_CPUFREQ
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select ARCH_SUPPORTS_MSI
select ARM_AMBA
select CLKSRC_OF
select USE_OF
select COMMON_CLK_SAMSUNG
select CLKSRC_EXYNOS_MCT
select PINCTRL
config ARCH_EXYNOS8
bool "ARMv8 based Samsung Exynos8"
select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
Samsung EXYNOS8 (Mongoose/A53) SoC based systems
config SOC_EXYNOS9810
bool "Samsung EXYNOS9810"
select SOC_SAMSUNG
select ARCH_EXYNOS
select ARCH_HAS_CPUFREQ
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select ARCH_SUPPORTS_MSI
select ARM_AMBA
select CLKSRC_OF
select USE_OF
select COMMON_CLK_SAMSUNG
select CLKSRC_EXYNOS_MCT
select PINCTRL
select SAMSUNG_DMADEV
config SOC_EXYNOS9810_EVT1
bool "Samsung EXYNOS9810_EVT1"
depends on SOC_EXYNOS9810
config ARCH_EXYNOS9
bool "ARMv8 based Samsung Exynos9"
select HAVE_ARM_SCU if SMP
select HAVE_SMP
help
Samsung EXYNOS9 (Meercat/Ananke) SoC based systems
config ZONE_MOVABLE
bool "Enable Zone Movable"
default n
config ZONE_MOVABLE_SIZE_MBYTES
int "ZONE_MOVABLE Size in MBytes"
range 0 1024
default 0
depends on ZONE_MOVABLE
help
Set Movable Zone size based on bits shift value. Movable Zone size
must be less than the highest populated zone.
endmenu
endmenu

7
arch/arm64/Makefile
View file

@ -22,6 +22,10 @@ LDFLAGS_vmlinux += -pie -shared -Bsymbolic \
$(call ld-option, --no-apply-dynamic-relocs)
endif
ifneq ($(CONFIG_RELOCATABLE_KERNEL),)
LDFLAGS_vmlinux += -pie -Bsymbolic
endif
ifeq ($(CONFIG_ARM64_ERRATUM_843419),y)
ifeq ($(call ld-option, --fix-cortex-a53-843419),)
$(warning ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum)
@ -147,6 +151,9 @@ zinstall install:
%.dtb: scripts
$(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
%.dtbo: scripts
$(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
PHONY += dtbs dtbs_install
dtbs: prepare scripts

2
arch/arm64/boot/Makefile
View file

@ -24,7 +24,7 @@ DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES))
ifneq ($(DTB_NAMES),)
DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES))
else
DTB_LIST := $(dtb-y)
DTB_LIST := $(dtb-y) $(dtbo-y)
endif
DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST))

1
arch/arm64/boot/dts/.gitignore vendored
View file

@ -1 +0,0 @@
*.dtb

49
arch/arm64/boot/dts/Makefile
View file

@ -1,44 +1,15 @@
dts-dirs += al
dts-dirs += altera
dts-dirs += amd
dts-dirs += amlogic
dts-dirs += apm
dts-dirs += arm
dts-dirs += broadcom
dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += hisilicon
dts-dirs += marvell
dts-dirs += mediatek
dts-dirs += nvidia
dts-dirs += qcom
dts-dirs += renesas
dts-dirs += rockchip
dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
dts-dirs += lg
dts-dirs += zte
subdir-y := $(dts-dirs)
dtstree := $(srctree)/$(src)
dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(foreach d,$(dts-dirs), $(wildcard $(dtstree)/$(d)/*.dts)))
always := $(dtb-y)
# SPDX-License-Identifier: GPL-2.0
dtb-y += exynos/exynos9810-star2lte_eur_open_16.dtb
dtb-y += exynos/exynos9810-star2lte_eur_open_17.dtb
dtb-y += exynos/exynos9810-star2lte_eur_open_18.dtb
dtb-y += exynos/exynos9810-star2lte_eur_open_20.dtb
dtb-y += exynos/exynos9810-star2lte_eur_open_23.dtb
dtb-y += exynos/exynos9810-star2lte_eur_open_26.dtb
targets += dtbs
DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES))
ifneq ($(DTB_NAMES),)
DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES))
else
DTB_LIST := $(dtb-y)
endif
targets += $(DTB_LIST)
DTB_LIST := $(dtb-y) $(dtbo-y)
always := $(DTB_LIST)
dtbs: $(addprefix $(obj)/, $(DTB_LIST))
clean-files := dts/*.dtb *.dtb
clean-files := *.dtb*

5
arch/arm64/boot/dts/al/Makefile
View file

@ -1,5 +0,0 @@
dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

53
arch/arm64/boot/dts/al/alpine-v2-evp.dts
View file

@ -1,53 +0,0 @@
/*
* Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Antoine Tenart <antoine.tenart@free-electrons.com>
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "alpine-v2.dtsi"
/ {
model = "Annapurna Labs Alpine v2 EVP";
compatible = "al,alpine-v2-evp", "al,alpine-v2";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 { status = "okay"; };

236
arch/arm64/boot/dts/al/alpine-v2.dtsi
View file

@ -1,236 +0,0 @@
/*
* Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Antoine Tenart <antoine.tenart@free-electrons.com>
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Annapurna Labs Alpine v2";
compatible = "al,alpine-v2";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2", "arm,psci";
method = "smc";
cpu_suspend = <0x84000001>;
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
sbclk: sbclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
ranges;
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
gic: gic@f0100000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */
<0x0 0xf0280000 0x0 0x200000>, /* GICR */
<0x0 0xf0100000 0x0 0x2000>, /* GICC */
<0x0 0xf0110000 0x0 0x2000>, /* GICV */
<0x0 0xf0120000 0x0 0x2000>; /* GICH */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
pci@fbc00000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
#interrupt-cells = <1>;
reg = <0x0 0xfbc00000 0x0 0x100000>;
interrupt-map-mask = <0xf800 0 0 7>;
/* add legacy interrupts for SATA only */
interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
<0x4800 0 0 1 &gic 0 54 4>;
/* 32 bit non prefetchable memory space */
ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
msi-parent = <&msix>;
};
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;
};
io-fabric {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xfc000000 0x2000000>;
uart0: serial@1883000 {
compatible = "ns16550a";
device_type = "serial";
reg = <0x1883000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@1884000 {
compatible = "ns16550a";
device_type = "serial";
reg = <0x1884000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@1885000 {
compatible = "ns16550a";
device_type = "serial";
reg = <0x1885000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@1886000 {
compatible = "ns16550a";
device_type = "serial";
reg = <0x1886000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
timer0: timer@1890000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x1890000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sbclk>;
};
timer1: timer@1891000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x1891000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sbclk>;
status = "disabled";
};
timer2: timer@1892000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x1892000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sbclk>;
status = "disabled";
};
timer3: timer@1893000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x1893000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sbclk>;
status = "disabled";
};
};
};
};

5
arch/arm64/boot/dts/altera/Makefile
View file

@ -1,5 +0,0 @@
dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

358
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View file

@ -1,358 +0,0 @@
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
/ {
compatible = "altr,socfpga-stratix10";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 120 8>,
<0 121 8>,
<0 122 8>,
<0 123 8>;
interrupt-affinity = <&cpu0>,
<&cpu1>,
<&cpu2>,
<&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
intc: intc@fffc1000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0xfffc1000 0x1000>,
<0x0 0xfffc2000 0x2000>,
<0x0 0xfffc4000 0x2000>,
<0x0 0xfffc6000 0x2000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
clkmgr@ffd1000 {
compatible = "altr,clk-mgr";
reg = <0xffd10000 0x1000>;
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
status = "disabled";
};
gpio0: gpio@ffc03200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03200 0x100>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
};
};
gpio1: gpio@ffc03300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc03300 0x100>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 110 4>;
};
};
i2c0: i2c@ffc02800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02800 0x100>;
interrupts = <0 103 4>;
status = "disabled";
};
i2c1: i2c@ffc02900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02900 0x100>;
interrupts = <0 104 4>;
status = "disabled";
};
i2c2: i2c@ffc02a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>;
status = "disabled";
};
i2c3: i2c@ffc02b00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>;
status = "disabled";
};
i2c4: i2c@ffc02c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>;
status = "disabled";
};
mmc: dwmmc0@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0 96 4>;
fifo-depth = <0x400>;
status = "disabled";
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
};
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
};
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda4000 0x1000>;
interrupts = <0 101 4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
spi1: spi@ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x1000>;
interrupts = <0 102 4>;
num-chipselect = <4>;
bus-num = <0>;
status = "disabled";
};
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x1000>;
};
/* Local timer */
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>;
reg = <0xffc03000 0x100>;
};
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>;
reg = <0xffc03100 0x100>;
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>;
reg = <0xffd00000 0x100>;
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>;
reg = <0xffd00100 0x100>;
};
uart0: serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 108 4>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial1@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 109 4>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
};
watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
status = "disabled";
};
watchdog2: watchdog@ffd00400 {
compatible = "snps,dw-wdt";
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
status = "disabled";
};
watchdog3: watchdog@ffd00500 {
compatible = "snps,dw-wdt";
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
status = "disabled";
};
};
};

39
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View file

@ -1,39 +0,0 @@
/*
* Copyright Altera Corporation (C) 2015. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/include/ "socfpga_stratix10.dtsi"
/ {
model = "SoCFPGA Stratix 10 SoCDK";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
};
&uart0 {
status = "okay";
};

7
arch/arm64/boot/dts/amd/Makefile
View file

@ -1,7 +0,0 @@
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
husky.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

87
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts
View file

@ -1,87 +0,0 @@
/*
* DTS file for AMD Seattle Overdrive Development Board
* Note: For Seattle Rev.B0
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*/
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/ {
model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
compatible = "amd,seattle-overdrive", "amd,seattle";
chosen {
stdout-path = &serial0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
};
&ccp0 {
status = "ok";
amd,zlib-support = <1>;
};
/**
* NOTE: In Rev.B, gpio0 is reserved.
*/
&gpio1 {
status = "ok";
};
&gpio2 {
status = "ok";
};
&gpio3 {
status = "ok";
};
&gpio4 {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&spi0 {
status = "ok";
};
&spi1 {
status = "ok";
sdcard0: sdcard@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <20000000>;
voltage-ranges = <3200 3400>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,com-mode = <0x0>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
};
};
&ipmi_kcs {
status = "ok";
};
&smb0 {
/include/ "amd-seattle-xgbe-b.dtsi"
};

91
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts
View file

@ -1,91 +0,0 @@
/*
* DTS file for AMD Seattle Overdrive Development Board
* Note: For Seattle Rev.B1
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*/
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/ {
model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
compatible = "amd,seattle-overdrive", "amd,seattle";
chosen {
stdout-path = &serial0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
};
&ccp0 {
status = "ok";
amd,zlib-support = <1>;
};
/**
* NOTE: In Rev.B, gpio0 is reserved.
*/
&gpio1 {
status = "ok";
};
&gpio2 {
status = "ok";
};
&gpio3 {
status = "ok";
};
&gpio4 {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&sata1 {
status = "ok";
};
&spi0 {
status = "ok";
};
&spi1 {
status = "ok";
sdcard0: sdcard@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <20000000>;
voltage-ranges = <3200 3400>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,com-mode = <0x0>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
};
};
&ipmi_kcs {
status = "ok";
};
&smb0 {
/include/ "amd-seattle-xgbe-b.dtsi"
};

65
arch/arm64/boot/dts/amd/amd-overdrive.dts
View file

@ -1,65 +0,0 @@
/*
* DTS file for AMD Seattle Overdrive Development Board
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*/
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/ {
model = "AMD Seattle Development Board (Overdrive)";
compatible = "amd,seattle-overdrive", "amd,seattle";
chosen {
stdout-path = &serial0;
};
};
&ccp0 {
status = "ok";
};
&gpio0 {
status = "ok";
};
&gpio1 {
status = "ok";
};
&i2c0 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&spi0 {
status = "ok";
};
&spi1 {
status = "ok";
sdcard0: sdcard@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <20000000>;
voltage-ranges = <3200 3400>;
gpios = <&gpio0 7 0>;
interrupt-parent = <&gpio0>;
interrupts = <7 3>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,com-mode = <0x0>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
};
};
&v2m0 {
arm,msi-base-spi = <64>;
arm,msi-num-spis = <256>;
};

54
arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
View file

@ -1,54 +0,0 @@
/*
* DTS file for AMD Seattle Clocks
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*/
adl3clk_100mhz: clk100mhz_0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "adl3clk_100mhz";
};
ccpclk_375mhz: clk375mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <375000000>;
clock-output-names = "ccpclk_375mhz";
};
sataclk_333mhz: clk333mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <333000000>;
clock-output-names = "sataclk_333mhz";
};
pcieclk_500mhz: clk500mhz_0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "pcieclk_500mhz";
};
dmaclk_500mhz: clk500mhz_1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "dmaclk_500mhz";
};
miscclk_250mhz: clk250mhz_4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "miscclk_250mhz";
};
uartspiclk_100mhz: clk100mhz_1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "uartspiclk_100mhz";
};

250
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
View file

@ -1,250 +0,0 @@
/*
* DTS file for AMD Seattle SoC
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*/
/ {
compatible = "amd,seattle";
interrupt-parent = <&gic0>;
#address-cells = <2>;
#size-cells = <2>;
gic0: interrupt-controller@e1101000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xe1110000 0 0x1000>,
<0x0 0xe112f000 0 0x2000>,
<0x0 0xe1140000 0 0x2000>,
<0x0 0xe1160000 0 0x2000>;
interrupts = <1 9 0xf04>;
ranges = <0 0 0 0xe1100000 0 0x100000>;
v2m0: v2m@e0080000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x00080000 0 0x1000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff04>,
<1 14 0xff04>,
<1 11 0xff04>,
<1 10 0xff04>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 7 4>,
<0 8 4>,
<0 9 4>,
<0 10 4>,
<0 11 4>,
<0 12 4>,
<0 13 4>,
<0 14 4>;
};
smb0: smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* dma-ranges is 40-bit address space containing:
* - GICv2m MSI register is at 0xe0080000
* - DRAM range [0x8000000000 to 0xffffffffff]
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
/include/ "amd-seattle-clks.dtsi"
sata0: sata@e0300000 {
compatible = "snps,dwc-ahci";
reg = <0 0xe0300000 0 0xf0000>;
interrupts = <0 355 4>;
clocks = <&sataclk_333mhz>;
dma-coherent;
};
/* This is for Rev B only */
sata1: sata@e0d00000 {
status = "disabled";
compatible = "snps,dwc-ahci";
reg = <0 0xe0d00000 0 0xf0000>;
interrupts = <0 354 4>;
clocks = <&sataclk_333mhz>;
dma-coherent;
};
i2c0: i2c@e1000000 {
status = "disabled";
compatible = "snps,designware-i2c";
reg = <0 0xe1000000 0 0x1000>;
interrupts = <0 357 4>;
clocks = <&miscclk_250mhz>;
};
i2c1: i2c@e0050000 {
status = "disabled";
compatible = "snps,designware-i2c";
reg = <0 0xe0050000 0 0x1000>;
interrupts = <0 340 4>;
clocks = <&miscclk_250mhz>;
};
serial0: serial@e1010000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0xe1010000 0 0x1000>;
interrupts = <0 328 4>;
clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
clock-names = "uartclk", "apb_pclk";
};
spi0: ssp@e1020000 {
status = "disabled";
compatible = "arm,pl022", "arm,primecell";
reg = <0 0xe1020000 0 0x1000>;
spi-controller;
interrupts = <0 330 4>;
clocks = <&uartspiclk_100mhz>;
clock-names = "apb_pclk";
};
spi1: ssp@e1030000 {
status = "disabled";
compatible = "arm,pl022", "arm,primecell";
reg = <0 0xe1030000 0 0x1000>;
spi-controller;
interrupts = <0 329 4>;
clocks = <&uartspiclk_100mhz>;
clock-names = "apb_pclk";
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
gpio0: gpio@e1040000 { /* Not available to OS for B0 */
status = "disabled";
compatible = "arm,pl061", "arm,primecell";
#gpio-cells = <2>;
reg = <0 0xe1040000 0 0x1000>;
gpio-controller;
interrupts = <0 359 4>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&miscclk_250mhz>;
clock-names = "apb_pclk";
};
gpio1: gpio@e1050000 { /* [0:7] */
status = "disabled";
compatible = "arm,pl061", "arm,primecell";
#gpio-cells = <2>;
reg = <0 0xe1050000 0 0x1000>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 358 4>;
clocks = <&miscclk_250mhz>;
clock-names = "apb_pclk";
};
gpio2: gpio@e0020000 { /* [8:15] */
status = "disabled";
compatible = "arm,pl061", "arm,primecell";
#gpio-cells = <2>;
reg = <0 0xe0020000 0 0x1000>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 366 4>;
clocks = <&miscclk_250mhz>;
clock-names = "apb_pclk";
};
gpio3: gpio@e0030000 { /* [16:23] */
status = "disabled";
compatible = "arm,pl061", "arm,primecell";
#gpio-cells = <2>;
reg = <0 0xe0030000 0 0x1000>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 365 4>;
clocks = <&miscclk_250mhz>;
clock-names = "apb_pclk";
};
gpio4: gpio@e0080000 { /* [24] */
status = "disabled";
compatible = "arm,pl061", "arm,primecell";
#gpio-cells = <2>;
reg = <0 0xe0080000 0 0x1000>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 361 4>;
clocks = <&miscclk_250mhz>;
clock-names = "apb_pclk";
};
ccp0: ccp@e0100000 {
status = "disabled";
compatible = "amd,ccp-seattle-v1a";
reg = <0 0xe0100000 0 0x10000>;
interrupts = <0 3 4>;
dma-coherent;
};
pcie0: pcie@f0000000 {
compatible = "pci-host-ecam-generic";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
bus-range = <0 0x7f>;
msi-parent = <&v2m0>;
reg = <0 0xf0000000 0 0x10000000>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map =
<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
dma-coherent;
dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
ranges =
/* I/O Memory (size=64K) */
<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
/* 32-bit MMIO (size=2G) */
<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
/* 64-bit MMIO (size= 124G) */
<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
};
/* Perf CCN504 PMU */
ccn: ccn@e8000000 {
compatible = "arm,ccn-504";
reg = <0x0 0xe8000000 0 0x1000000>;
interrupts = <0 380 4>;
};
ipmi_kcs: kcs@e0010000 {
status = "disabled";
compatible = "ipmi-kcs";
device_type = "ipmi";
reg = <0x0 0xe0010000 0 0x8>;
interrupts = <0 389 4>;
reg-size = <1>;
reg-spacing = <4>;
};
};
};

117
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi
View file

@ -1,117 +0,0 @@
/*
* DTS file for AMD Seattle XGBE (RevB)
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*/
xgmacclk0_dma_250mhz: clk250mhz_0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "xgmacclk0_dma_250mhz";
};
xgmacclk0_ptp_250mhz: clk250mhz_1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "xgmacclk0_ptp_250mhz";
};
xgmacclk1_dma_250mhz: clk250mhz_2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "xgmacclk1_dma_250mhz";
};
xgmacclk1_ptp_250mhz: clk250mhz_3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "xgmacclk1_ptp_250mhz";
};
xgmac0: xgmac@e0700000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0700000 0 0x80000>,
<0 0xe0780000 0 0x80000>,
<0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
<0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 325 4>,
<0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
<0 323 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 A1 A2 A3 A4 A5 ];
clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
#stream-id-cells = <16>;
dma-coherent;
};
xgmac1: xgmac@e0900000 {
compatible = "amd,xgbe-seattle-v1a";
reg = <0 0xe0900000 0 0x80000>,
<0 0xe0980000 0 0x80000>,
<0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
<0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
<0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
interrupts = <0 324 4>,
<0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
<0 322 4>;
amd,per-channel-interrupt;
amd,speed-set = <0>;
amd,serdes-blwc = <1>, <1>, <0>;
amd,serdes-cdr-rate = <2>, <2>, <7>;
amd,serdes-pq-skew = <10>, <10>, <18>;
amd,serdes-tx-amp = <0>, <0>, <0>;
amd,serdes-dfe-tap-config = <3>, <3>, <3>;
amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
mac-address = [ 02 B1 B2 B3 B4 B5 ];
clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
clock-names = "dma_clk", "ptp_clk";
phy-mode = "xgmii";
#stream-id-cells = <16>;
dma-coherent;
};
xgmac0_smmu: smmu@e0600000 {
compatible = "arm,mmu-401";
reg = <0 0xe0600000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 336 4>,
<0 336 4>;
mmu-masters = <&xgmac0
0 1 2 3 4 5 6 7
16 17 18 19 20 21 22 23
>;
};
xgmac1_smmu: smmu@e0800000 {
compatible = "arm,mmu-401";
reg = <0 0xe0800000 0 0x10000>;
#global-interrupts = <1>;
interrupts = /* Uses combined intr for both
* global and context
*/
<0 335 4>,
<0 335 4>;
mmu-masters = <&xgmac1
0 1 2 3 4 5 6 7
16 17 18 19 20 21 22 23
>;
};

83
arch/arm64/boot/dts/amd/husky.dts
View file

@ -1,83 +0,0 @@
/*
* DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board
* Note: Based-on AMD Seattle Rev.B0
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
*/
/dts-v1/;
/include/ "amd-seattle-soc.dtsi"
/ {
model = "Linaro 96Boards Enterprise Edition Server (Husky) Board";
compatible = "amd,seattle-overdrive", "amd,seattle";
chosen {
stdout-path = &serial0;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
};
&ccp0 {
status = "ok";
amd,zlib-support = <1>;
};
/**
* NOTE: In Rev.B, gpio0 is reserved.
*/
&gpio1 {
status = "ok";
};
&gpio2 {
status = "ok";
};
&gpio3 {
status = "ok";
};
&gpio4 {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&spi0 {
status = "ok";
};
&spi1 {
status = "ok";
sdcard0: sdcard@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <20000000>;
voltage-ranges = <3200 3400>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,com-mode = <0x0>;
pl022,rx-level-trig = <0>;
pl022,tx-level-trig = <0>;
};
};
&smb0 {
/include/ "amd-seattle-xgbe-b.dtsi"
};

10
arch/arm64/boot/dts/amlogic/Makefile
View file

@ -1,10 +0,0 @@
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

112
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View file

@ -1,112 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
leds {
compatible = "gpio-leds";
blue {
label = "c2:blue:alive";
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
phy-handle = <&eth_phy0>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
eth_phy0: ethernet-phy@0 {
reg = <0>;
eee-broken-1000t;
};
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&i2c_A {
status = "okay";
pinctrl-0 = <&i2c_a_pins>;
pinctrl-names = "default";
};

58
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
View file

@ -1,58 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p200", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P200 Development Board";
};
&i2c_B {
status = "okay";
pinctrl-0 = <&i2c_b_pins>;
pinctrl-names = "default";
};

52
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
View file

@ -1,52 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-p20x.dtsi"
/ {
compatible = "amlogic,p201", "amlogic,meson-gxbb";
model = "Amlogic Meson GXBB P201 Development Board";
};

109
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View file

@ -1,109 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
* Copyright (c) 2016 BayLibre, Inc.
* Author: Kevin Hilman <khilman@kernel.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxbb.dtsi"
/ {
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
usb_pwr: regulator-usb-pwrs {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
/* signal name in schematic: USB_PWR_EN */
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
/* This UART is brought out to the DB9 connector */
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_pwr>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

55
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
View file

@ -1,55 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-vega-s95.dtsi"
/ {
compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Meta";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};

55
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
View file

@ -1,55 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-vega-s95.dtsi"
/ {
compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Pro";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};

55
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
View file

@ -1,55 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "meson-gxbb-vega-s95.dtsi"
/ {
compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb";
model = "Tronsmart Vega S95 Telos";
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};

104
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
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@ -1,104 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "meson-gxbb.dtsi"
/ {
compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
usb_vbus: regulator-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "USB0_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_pins>;
pinctrl-names = "default";
};
&usb0_phy {
status = "okay";
phy-supply = <&usb_vbus>;
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

669
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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@ -1,669 +0,0 @@
/*
* Copyright (c) 2016 Andreas Färber
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>
/ {
compatible = "amlogic,meson-gxbb";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
firmware {
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
};
};
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
#address-cells = <1>;
#size-cells = <1>;
sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
reg = <0x34 0x10>;
};
bid: bid@46 {
reg = <0x46 0x30>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0_phy: phy@c0000000 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0xc0000000 0x0 0x20>;
resets = <&reset RESET_USB_OTG>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
clock-names = "usb_general", "usb";
status = "disabled";
};
usb1_phy: phy@c0000020 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0xc0000020 0x0 0x20>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
clock-names = "usb_general", "usb";
status = "disabled";
};
cbus: cbus@c1100000 {
compatible = "simple-bus";
reg = <0x0 0xc1100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
reset: reset-controller@4404 {
compatible = "amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
#reset-cells = <1>;
};
uart_A: serial@84c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84c0 0x0 0x14>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
uart_B: serial@84dc {
compatible = "amlogic,meson-uart";
reg = <0x0 0x84dc 0x0 0x14>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
pwm_ab: pwm@8550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@8650 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x08650 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_ef: pwm@86c0 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x086c0 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
uart_C: serial@8700 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x8700 0x0 0x14>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x0 0x098d0 0x0 0x10>;
clocks = <&xtal>;
};
spifc: spi@8c80 {
compatible = "amlogic,meson-gxbb-spifc";
reg = <0x0 0x08c80 0x0 0x80>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SPI>;
status = "disabled";
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x08500 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087c0 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_C: i2c@87e0 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x087e0 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gic: interrupt-controller@c4301000 {
compatible = "arm,gic-400";
reg = <0x0 0xc4301000 0 0x1000>,
<0x0 0xc4302000 0 0x2000>,
<0x0 0xc4304000 0 0x2000>,
<0x0 0xc4306000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
aobus: aobus@c8100000 {
compatible = "simple-bus";
reg = <0x0 0xc8100000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
pinctrl_aobus: pinctrl@14 {
compatible = "amlogic,meson-gxbb-aobus-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
};
};
remote_input_ao_pins: remote_input_ao {
mux {
groups = "remote_input_ao";
function = "remote_input_ao";
};
};
i2c_ao_pins: i2c_ao {
mux {
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
};
};
pwm_ao_a_3_pins: pwm_ao_a_3 {
mux {
groups = "pwm_ao_a_3";
function = "pwm_ao_a_3";
};
};
pwm_ao_a_6_pins: pwm_ao_a_6 {
mux {
groups = "pwm_ao_a_6";
function = "pwm_ao_a_6";
};
};
pwm_ao_a_12_pins: pwm_ao_a_12 {
mux {
groups = "pwm_ao_a_12";
function = "pwm_ao_a_12";
};
};
pwm_ao_b_pins: pwm_ao_b {
mux {
groups = "pwm_ao_b";
function = "pwm_ao_b";
};
};
};
clkc_AO: clock-controller@040 {
compatible = "amlogic,gxbb-aoclkc";
reg = <0x0 0x00040 0x0 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
uart_AO: serial@4c0 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x004c0 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
};
ir: ir@580 {
compatible = "amlogic,meson-gxbb-ir";
reg = <0x0 0x00580 0x0 0x40>;
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pwm_ab_AO: pwm@550 {
compatible = "amlogic,meson-gxbb-pwm";
reg = <0x0 0x0550 0x0 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson-gxbb-i2c";
reg = <0x0 0x500 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
periphs: periphs@c8834000 {
compatible = "simple-bus";
reg = <0x0 0xc8834000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x0 0x0 0x4>;
};
pinctrl_periphs: pinctrl@4b0 {
compatible = "amlogic,meson-gxbb-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4b0 {
reg = <0x0 0x004b0 0x0 0x28>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00120 0x0 0x14>,
<0x0 0x00430 0x0 0x40>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d07",
"emmc_cmd",
"emmc_clk";
function = "emmc";
};
};
nor_pins: nor {
mux {
groups = "nor_d",
"nor_q",
"nor_c",
"nor_cs";
function = "nor";
};
};
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd",
"sdcard_clk";
function = "sdcard";
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
function = "sdio";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_b_pins: uart_b {
mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
};
};
uart_c_pins: uart_c {
mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
};
};
i2c_a_pins: i2c_a {
mux {
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
};
};
i2c_b_pins: i2c_b {
mux {
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
};
};
i2c_c_pins: i2c_c {
mux {
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
};
};
eth_pins: eth_c {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_clk_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_rxd2",
"eth_rxd3",
"eth_rgmii_tx_clk",
"eth_tx_en",
"eth_txd0",
"eth_txd1",
"eth_txd2",
"eth_txd3";
function = "eth";
};
};
pwm_a_x_pins: pwm_a_x {
mux {
groups = "pwm_a_x";
function = "pwm_a_x";
};
};
pwm_a_y_pins: pwm_a_y {
mux {
groups = "pwm_a_y";
function = "pwm_a_y";
};
};
pwm_b_pins: pwm_b {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
pwm_d_pins: pwm_d {
mux {
groups = "pwm_d";
function = "pwm_d";
};
};
pwm_e_pins: pwm_e {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
pwm_f_x_pins: pwm_f_x {
mux {
groups = "pwm_f_x";
function = "pwm_f_x";
};
};
pwm_f_y_pins: pwm_f_y {
mux {
groups = "pwm_f_y";
function = "pwm_f_y";
};
};
};
};
hiubus: hiubus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
clkc: clock-controller@0 {
compatible = "amlogic,gxbb-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0x3db>;
};
mailbox: mailbox@404 {
compatible = "amlogic,meson-gxbb-mhu";
reg = <0 0x404 0 0x4c>;
interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
<0 209 IRQ_TYPE_EDGE_RISING>,
<0 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
};
apb: apb@d0000000 {
compatible = "simple-bus";
reg = <0x0 0xd0000000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
};
usb0: usb@c9000000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9000000 0x0 0x40000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb0_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
usb1: usb@c9100000 {
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
reg = <0x0 0xc9100000 0x0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
clock-names = "otg";
phys = <&usb1_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000
0x0 0xc8834540 0x0 0x4>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
status = "disabled";
};
};
};

6
arch/arm64/boot/dts/apm/Makefile
View file

@ -1,6 +0,0 @@
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

91
arch/arm64/boot/dts/apm/apm-merlin.dts
View file

@ -1,91 +0,0 @@
/*
* dts file for AppliedMicro (APM) Merlin Board
*
* Copyright (C) 2015, Applied Micro Circuits Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/dts-v1/;
/include/ "apm-shadowcat.dtsi"
/ {
model = "APM X-Gene Merlin board";
compatible = "apm,merlin", "apm,xgene-shadowcat";
chosen { };
memory {
device_type = "memory";
reg = < 0x1 0x00000000 0x0 0x80000000 >;
};
gpio-keys {
compatible = "gpio-keys";
button@1 {
label = "POWER";
linux,code = <116>;
linux,input-type = <0x1>;
interrupt-parent = <&sbgpio>;
interrupts = <0x0 0x1>;
};
};
poweroff_mbox: poweroff_mbox@10548000 {
compatible = "syscon";
reg = <0x0 0x10548000 0x0 0x30>;
};
poweroff: poweroff@10548010 {
compatible = "syscon-poweroff";
regmap = <&poweroff_mbox>;
offset = <0x10>;
mask = <0x1>;
};
};
&serial0 {
status = "ok";
};
&sata1 {
status = "ok";
};
&sata2 {
status = "ok";
};
&sata3 {
status = "ok";
};
&sgenet0 {
status = "ok";
};
&xgenet1 {
status = "ok";
};
&mmc0 {
status = "ok";
};
&i2c4 {
rtc68: rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
status = "ok";
};
};
&mdio {
sgenet0phy: phy@0 {
reg = <0x0>;
};
};

94
arch/arm64/boot/dts/apm/apm-mustang.dts
View file

@ -1,94 +0,0 @@
/*
* dts file for AppliedMicro (APM) Mustang Board
*
* Copyright (C) 2013, Applied Micro Circuits Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/dts-v1/;
/include/ "apm-storm.dtsi"
/ {
model = "APM X-Gene Mustang board";
compatible = "apm,mustang", "apm,xgene-storm";
chosen { };
memory {
device_type = "memory";
reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
};
gpio-keys {
compatible = "gpio-keys";
button@1 {
label = "POWER";
linux,code = <116>;
linux,input-type = <0x1>;
interrupt-parent = <&sbgpio>;
interrupts = <0x5 0x1>;
};
};
poweroff_mbox: poweroff_mbox@10548000 {
compatible = "syscon";
reg = <0x0 0x10548000 0x0 0x30>;
};
poweroff: poweroff@10548010 {
compatible = "syscon-poweroff";
regmap = <&poweroff_mbox>;
offset = <0x10>;
mask = <0x1>;
};
};
&pcie0clk {
status = "ok";
};
&pcie0 {
status = "ok";
};
&serial0 {
status = "ok";
};
&menet {
status = "ok";
};
&sgenet0 {
status = "ok";
};
&sgenet1 {
status = "ok";
};
&xgenet {
status = "ok";
rxlos-gpios = <&sbgpio 12 1>;
};
&mmc0 {
status = "ok";
};
&mdio {
menet0phy: phy@3 {
reg = <0x3>;
};
sgenet0phy: phy@4 {
reg = <0x4>;
};
sgenet1phy: phy@5 {
reg = <0x5>;
};
};

820
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
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@ -1,820 +0,0 @@
/*
* dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
*
* Copyright (C) 2015, Applied Micro Circuits Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/ {
compatible = "apm,xgene-shadowcat";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
#clock-cells = <1>;
clocks = <&pmd0clk 0>;
};
cpu@001 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
#clock-cells = <1>;
clocks = <&pmd0clk 0>;
};
cpu@100 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
#clock-cells = <1>;
clocks = <&pmd1clk 0>;
};
cpu@101 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
#clock-cells = <1>;
clocks = <&pmd1clk 0>;
};
cpu@200 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
#clock-cells = <1>;
clocks = <&pmd2clk 0>;
};
cpu@201 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x201>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
#clock-cells = <1>;
clocks = <&pmd2clk 0>;
};
cpu@300 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
#clock-cells = <1>;
clocks = <&pmd3clk 0>;
};
cpu@301 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
reg = <0x0 0x301>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
#clock-cells = <1>;
clocks = <&pmd3clk 0>;
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
};
};
gic: interrupt-controller@78090000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
<0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
<0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
<0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
v2m0: v2m@00000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0x1000>;
};
v2m1: v2m@10000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x10000 0x0 0x1000>;
};
v2m2: v2m@20000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x20000 0x0 0x1000>;
};
v2m3: v2m@30000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x30000 0x0 0x1000>;
};
v2m4: v2m@40000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x40000 0x0 0x1000>;
};
v2m5: v2m@50000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x50000 0x0 0x1000>;
};
v2m6: v2m@60000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x60000 0x0 0x1000>;
};
v2m7: v2m@70000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x70000 0x0 0x1000>;
};
v2m8: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0x0 0x1000>;
};
v2m9: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0x0 0x1000>;
};
v2m10: v2m@a0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xa0000 0x0 0x1000>;
};
v2m11: v2m@b0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xb0000 0x0 0x1000>;
};
v2m12: v2m@c0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xc0000 0x0 0x1000>;
};
v2m13: v2m@d0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xd0000 0x0 0x1000>;
};
v2m14: v2m@e0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xe0000 0x0 0x1000>;
};
v2m15: v2m@f0000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xf0000 0x0 0x1000>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 12 0xff04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff08>, /* Virt IRQ */
<1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <100000000>;
clock-output-names = "refclk";
};
pmdpll: pmdpll@170000f0 {
compatible = "apm,xgene-pcppll-v2-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
reg = <0x0 0x170000f0 0x0 0x10>;
clock-output-names = "pmdpll";
};
pmd0clk: pmd0clk@7e200200 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200200 0x0 0x10>;
clock-output-names = "pmd0clk";
};
pmd1clk: pmd1clk@7e200210 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200210 0x0 0x10>;
clock-output-names = "pmd1clk";
};
pmd2clk: pmd2clk@7e200220 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200220 0x0 0x10>;
clock-output-names = "pmd2clk";
};
pmd3clk: pmd3clk@7e200230 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200230 0x0 0x10>;
clock-output-names = "pmd3clk";
};
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-v2-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
reg = <0x0 0x17000120 0x0 0x1000>;
clock-output-names = "socpll";
};
socplldiv2: socplldiv2 {
compatible = "fixed-factor-clock";
#clock-cells = <1>;
clocks = <&socpll 0>;
clock-mult = <1>;
clock-div = <2>;
clock-output-names = "socplldiv2";
};
ahbclk: ahbclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x164>;
divider-width = <0x5>;
divider-shift = <0x0>;
clock-output-names = "ahbclk";
};
sbapbclk: sbapbclk@1704c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&ahbclk 0>;
reg = <0x0 0x1704c000 0x0 0x2000>;
reg-names = "div-reg";
divider-offset = <0x10>;
divider-width = <0x2>;
divider-shift = <0x0>;
clock-output-names = "sbapbclk";
};
sdioclk: sdioclk@1f2ac000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2ac000 0x0 0x1000
0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg", "div-reg";
csr-offset = <0x0>;
csr-mask = <0x2>;
enable-offset = <0x8>;
enable-mask = <0x2>;
divider-offset = <0x178>;
divider-width = <0x8>;
divider-shift = <0x0>;
clock-output-names = "sdioclk";
};
pcie0clk: pcie0clk@1f2bc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2bc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie0clk";
};
pcie1clk: pcie1clk@1f2cc000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f2cc000 0x0 0x1000>;
reg-names = "csr-reg";
clock-output-names = "pcie1clk";
};
xge0clk: xge0clk@1f61c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f61c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
csr-mask = <0x3>;
clock-output-names = "xge0clk";
};
xge1clk: xge1clk@1f62c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x1f62c000 0x0 0x1000>;
reg-names = "csr-reg";
enable-mask = <0x3>;
csr-mask = <0x3>;
clock-output-names = "xge1clk";
};
rngpkaclk: rngpkaclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&socplldiv2 0>;
reg = <0x0 0x17000000 0x0 0x2000>;
reg-names = "csr-reg";
csr-offset = <0xc>;
csr-mask = <0x10>;
enable-offset = <0x10>;
enable-mask = <0x10>;
clock-output-names = "rngpkaclk";
};
i2c4clk: i2c4clk@1704c000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
clocks = <&sbapbclk 0>;
reg = <0x0 0x1704c000 0x0 0x1000>;
reg-names = "csr-reg";
csr-offset = <0x0>;
csr-mask = <0x40>;
enable-offset = <0x8>;
enable-mask = <0x40>;
clock-output-names = "i2c4clk";
};
};
scu: system-clk-controller@17000000 {
compatible = "apm,xgene-scu","syscon";
reg = <0x0 0x17000000 0x0 0x400>;
};
reboot: reboot@17000014 {
compatible = "syscon-reboot";
regmap = <&scu>;
offset = <0x14>;
mask = <0x1>;
};
csw: csw@7e200000 {
compatible = "apm,xgene-csw", "syscon";
reg = <0x0 0x7e200000 0x0 0x1000>;
};
mcba: mcba@7e700000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e700000 0x0 0x1000>;
};
mcbb: mcbb@7e720000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e720000 0x0 0x1000>;
};
efuse: efuse@1054a000 {
compatible = "apm,xgene-efuse", "syscon";
reg = <0x0 0x1054a000 0x0 0x20>;
};
edac@78800000 {
compatible = "apm,xgene-edac";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
regmap-efuse = <&efuse>;
reg = <0x0 0x78800000 0x0 0x100>;
interrupts = <0x0 0x20 0x4>,
<0x0 0x21 0x4>,
<0x0 0x27 0x4>;
edacmc@7e800000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e800000 0x0 0x1000>;
memory-controller = <0>;
};
edacmc@7e840000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e840000 0x0 0x1000>;
memory-controller = <1>;
};
edacmc@7e880000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e880000 0x0 0x1000>;
memory-controller = <2>;
};
edacmc@7e8c0000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e8c0000 0x0 0x1000>;
memory-controller = <3>;
};
edacpmd@7c000000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c000000 0x0 0x200000>;
pmd-controller = <0>;
};
edacpmd@7c200000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c200000 0x0 0x200000>;
pmd-controller = <1>;
};
edacpmd@7c400000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c400000 0x0 0x200000>;
pmd-controller = <2>;
};
edacpmd@7c600000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c600000 0x0 0x200000>;
pmd-controller = <3>;
};
edacl3@7e600000 {
compatible = "apm,xgene-edac-l3-v2";
reg = <0x0 0x7e600000 0x0 0x1000>;
};
edacsoc@7e930000 {
compatible = "apm,xgene-edac-soc";
reg = <0x0 0x7e930000 0x0 0x1000>;
};
};
pmu: pmu@78810000 {
compatible = "apm,xgene-pmu-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
reg = <0x0 0x78810000 0x0 0x1000>;
interrupts = <0x0 0x22 0x4>;
pmul3c@7e610000 {
compatible = "apm,xgene-pmu-l3c";
reg = <0x0 0x7e610000 0x0 0x1000>;
};
pmuiob@7e940000 {
compatible = "apm,xgene-pmu-iob";
reg = <0x0 0x7e940000 0x0 0x1000>;
};
pmucmcb@7e710000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e710000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmcb@7e730000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e730000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e810000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e810000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmc@7e850000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e850000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e890000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e890000 0x0 0x1000>;
enable-bit-index = <2>;
};
pmucmc@7e8d0000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e8d0000 0x0 0x1000>;
enable-bit-index = <3>;
};
};
mailbox: mailbox@10540000 {
compatible = "apm,xgene-slimpro-mbox";
reg = <0x0 0x10540000 0x0 0x8000>;
#mbox-cells = <1>;
interrupts = <0x0 0x0 0x4
0x0 0x1 0x4
0x0 0x2 0x4
0x0 0x3 0x4
0x0 0x4 0x4
0x0 0x5 0x4
0x0 0x6 0x4
0x0 0x7 0x4>;
};
i2cslimpro {
compatible = "apm,xgene-slimpro-i2c";
mboxes = <&mailbox 0>;
};
hwmonslimpro {
compatible = "apm,xgene-slimpro-hwmon";
mboxes = <&mailbox 7>;
};
serial0: serial@10600000 {
device_type = "serial";
compatible = "ns16550";
reg = <0 0x10600000 0x0 0x1000>;
reg-shift = <2>;
clock-frequency = <10000000>;
interrupt-parent = <&gic>;
interrupts = <0x0 0x4c 0x4>;
};
/* Do not change dwusb name, coded for backward compatibility */
usb0: dwusb@19000000 {
status = "disabled";
compatible = "snps,dwc3";
reg = <0x0 0x19000000 0x0 0x100000>;
interrupts = <0x0 0x5d 0x4>;
dma-coherent;
dr_mode = "host";
};
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
dma-coherent;
clocks = <&pcie0clk 0>;
msi-parent = <&v2m0>;
};
pcie1: pcie@1f2c0000 {
status = "disabled";
device_type = "pci";
compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
dma-coherent;
clocks = <&pcie1clk 0>;
msi-parent = <&v2m0>;
};
sata1: sata@1a000000 {
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a000000 0x0 0x1000>,
<0x0 0x1f200000 0x0 0x1000>,
<0x0 0x1f20d000 0x0 0x1000>,
<0x0 0x1f20e000 0x0 0x1000>;
interrupts = <0x0 0x5a 0x4>;
dma-coherent;
};
sata2: sata@1a200000 {
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a200000 0x0 0x1000>,
<0x0 0x1f210000 0x0 0x1000>,
<0x0 0x1f21d000 0x0 0x1000>,
<0x0 0x1f21e000 0x0 0x1000>;
interrupts = <0x0 0x5b 0x4>;
dma-coherent;
};
sata3: sata@1a400000 {
compatible = "apm,xgene-ahci-v2";
reg = <0x0 0x1a400000 0x0 0x1000>,
<0x0 0x1f220000 0x0 0x1000>,
<0x0 0x1f22d000 0x0 0x1000>,
<0x0 0x1f22e000 0x0 0x1000>;
interrupts = <0x0 0x5c 0x4>;
dma-coherent;
};
mmc0: mmc@1c000000 {
compatible = "arasan,sdhci-4.9a";
reg = <0x0 0x1c000000 0x0 0x100>;
interrupts = <0x0 0x49 0x4>;
dma-coherent;
no-1-8-v;
clock-names = "clk_xin", "clk_ahb";
clocks = <&sdioclk 0>, <&ahbclk 0>;
};
gfcgpio: gpio@1f63c000 {
compatible = "apm,xgene-gpio";
reg = <0x0 0x1f63c000 0x0 0x40>;
gpio-controller;
#gpio-cells = <2>;
};
dwgpio: gpio@1c024000 {
compatible = "snps,dw-apb-gpio";
reg = <0x0 0x1c024000 0x0 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
snps,nr-gpios = <32>;
reg = <0>;
};
};
sbgpio: gpio@17001000{
compatible = "apm,xgene-gpio-sb";
reg = <0x0 0x17001000 0x0 0x400>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <0x0 0x28 0x1>,
<0x0 0x29 0x1>,
<0x0 0x2a 0x1>,
<0x0 0x2b 0x1>,
<0x0 0x2c 0x1>,
<0x0 0x2d 0x1>,
<0x0 0x2e 0x1>,
<0x0 0x2f 0x1>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
interrupt-controller;
apm,nr-gpios = <22>;
apm,nr-irqs = <8>;
apm,irq-start = <8>;
};
mdio: mdio@1f610000 {
compatible = "apm,xgene-mdio-xfi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1f610000 0x0 0xd100>;
clocks = <&xge0clk 0>;
};
sgenet0: ethernet@1f610000 {
compatible = "apm,xgene2-sgenet";
status = "disabled";
reg = <0x0 0x1f610000 0x0 0xd100>,
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x20000>;
interrupts = <0 96 4>,
<0 97 4>;
dma-coherent;
clocks = <&xge0clk 0>;
local-mac-address = [00 01 73 00 00 01];
phy-connection-type = "sgmii";
phy-handle = <&sgenet0phy>;
};
xgenet1: ethernet@1f620000 {
compatible = "apm,xgene2-xgenet";
status = "disabled";
reg = <0x0 0x1f620000 0x0 0x10000>,
<0x0 0x1f600000 0x0 0xd100>,
<0x0 0x20000000 0x0 0x220000>;
interrupts = <0 108 4>,
<0 109 4>,
<0 110 4>,
<0 111 4>,
<0 112 4>,
<0 113 4>,
<0 114 4>,
<0 115 4>;
channel = <12>;
port-id = <1>;
dma-coherent;
clocks = <&xge1clk 0>;
local-mac-address = [00 01 73 00 00 02];
phy-connection-type = "xgmii";
};
rng: rng@10520000 {
compatible = "apm,xgene-rng";
reg = <0x0 0x10520000 0x0 0x100>;
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
i2c1: i2c@10511000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10511000 0x0 0x1000>;
interrupts = <0 0x45 0x4>;
#clock-cells = <1>;
clocks = <&sbapbclk 0>;
bus_num = <1>;
};
i2c4: i2c@10640000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0x0 0x10640000 0x0 0x1000>;
interrupts = <0 0x3a 0x4>;
clocks = <&i2c4clk 0>;
bus_num = <4>;
};
};
};

1097
arch/arm64/boot/dts/apm/apm-storm.dtsi
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File diff suppressed because it is too large Load diff

8
arch/arm64/boot/dts/arm/Makefile
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@ -1,8 +0,0 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

30
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts
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@ -1,30 +0,0 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3 configuration)
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};

21
arch/arm64/boot/dts/arm/foundation-v8.dts
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@ -1,21 +0,0 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv2 configuration)
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
};

236
arch/arm64/boot/dts/arm/foundation-v8.dtsi
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@ -1,236 +0,0 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
/ {
model = "Foundation-v8A";
compatible = "arm,foundation-aarch64", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2a440000 0 0x1000>,
<0x0 0x2a450000 0 0x1000>;
interrupts = <0 27 4>;
timeout-sec = <30>;
};
smb@08000000 {
compatible = "arm,vexpress,v2m-p1", "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
<0 0 1 &gic 0 0 0 1 4>,
<0 0 2 &gic 0 0 0 2 4>,
<0 0 3 &gic 0 0 0 3 4>,
<0 0 4 &gic 0 0 0 4 4>,
<0 0 5 &gic 0 0 0 5 4>,
<0 0 6 &gic 0 0 0 6 4>,
<0 0 7 &gic 0 0 0 7 4>,
<0 0 8 &gic 0 0 0 8 4>,
<0 0 9 &gic 0 0 0 9 4>,
<0 0 10 &gic 0 0 0 10 4>,
<0 0 11 &gic 0 0 0 11 4>,
<0 0 12 &gic 0 0 0 12 4>,
<0 0 13 &gic 0 0 0 13 4>,
<0 0 14 &gic 0 0 0 14 4>,
<0 0 15 &gic 0 0 0 15 4>,
<0 0 16 &gic 0 0 0 16 4>,
<0 0 17 &gic 0 0 0 17 4>,
<0 0 18 &gic 0 0 0 18 4>,
<0 0 19 &gic 0 0 0 19 4>,
<0 0 20 &gic 0 0 0 20 4>,
<0 0 21 &gic 0 0 0 21 4>,
<0 0 22 &gic 0 0 0 22 4>,
<0 0 23 &gic 0 0 0 23 4>,
<0 0 24 &gic 0 0 0 24 4>,
<0 0 25 &gic 0 0 0 25 4>,
<0 0 26 &gic 0 0 0 26 4>,
<0 0 27 &gic 0 0 0 27 4>,
<0 0 28 &gic 0 0 0 28 4>,
<0 0 29 &gic 0 0 0 29 4>,
<0 0 30 &gic 0 0 0 30 4>,
<0 0 31 &gic 0 0 0 31 4>,
<0 0 32 &gic 0 0 0 32 4>,
<0 0 33 &gic 0 0 0 33 4>,
<0 0 34 &gic 0 0 0 34 4>,
<0 0 35 &gic 0 0 0 35 4>,
<0 0 36 &gic 0 0 0 36 4>,
<0 0 37 &gic 0 0 0 37 4>,
<0 0 38 &gic 0 0 0 38 4>,
<0 0 39 &gic 0 0 0 39 4>,
<0 0 40 &gic 0 0 0 40 4>,
<0 0 41 &gic 0 0 0 41 4>,
<0 0 42 &gic 0 0 0 42 4>;
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
};
};

641
arch/arm64/boot/dts/arm/juno-base.dtsi
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@ -1,641 +0,0 @@
/*
* Devices shared by all Juno boards
*/
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x2a810000 0x0 0x10000>;
clock-frequency = <50000000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
frame@2a830000 {
frame-number = <1>;
interrupts = <0 60 4>;
reg = <0x0 0x2a830000 0x0 0x10000>;
};
};
mailbox: mhu@2b1f0000 {
compatible = "arm,mhu", "arm,primecell";
reg = <0x0 0x2b1f0000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_lpri_rx",
"mhu_hpri_rx";
#mbox-cells = <1>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
};
gic: interrupt-controller@2c010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
reg = <0x0 0x2c010000 0 0x1000>,
<0x0 0x2c02f000 0 0x2000>,
<0x0 0x2c04f000 0 0x2000>,
<0x0 0x2c06f000 0 0x2000>;
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
ranges = <0 0 0 0x2c1c0000 0 0x40000>;
v2m_0: v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0 0 0 0x1000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
/*
* Juno TRMs specify the size for these coresight components as 64K.
* The actual size is just 4K though 64K is reserved. Access to the
* unmapped reserved region results in a DECERR response.
*/
etf@20010000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input port */
port@0 {
reg = <0>;
etf_in_port: endpoint {
slave-mode;
remote-endpoint = <&main_funnel_out_port>;
};
};
/* output port */
port@1 {
reg = <0>;
etf_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
};
tpiu@20030000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0x20030000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port0>;
};
};
};
main-funnel@20040000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x20040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
main_funnel_out_port: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
port@1 {
reg = <0>;
main_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_funnel_out_port>;
};
};
port@2 {
reg = <1>;
main_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_funnel_out_port>;
};
};
};
};
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x20070000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
};
};
};
etm0: etm@22040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
};
};
};
cluster0-funnel@220c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x220c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster0_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port0>;
};
};
port@1 {
reg = <0>;
cluster0_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm0_out_port>;
};
};
port@2 {
reg = <1>;
cluster0_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm1_out_port>;
};
};
};
};
etm1: etm@22140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x22140000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
};
};
};
etm2: etm@23040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23040000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
};
};
};
cluster1-funnel@230c0000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0x230c0000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster1_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port1>;
};
};
port@1 {
reg = <0>;
cluster1_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm0_out_port>;
};
};
port@2 {
reg = <1>;
cluster1_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm1_out_port>;
};
};
port@3 {
reg = <2>;
cluster1_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm2_out_port>;
};
};
port@4 {
reg = <3>;
cluster1_funnel_in_port3: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm3_out_port>;
};
};
};
};
etm3: etm@23140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23140000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
};
};
};
etm4: etm@23240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23240000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
};
};
};
etm5: etm@23340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x23340000 0 0x1000>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
};
};
};
coresight-replicator {
/*
* Non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
port@1 {
reg = <1>;
replicator_out_port1: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
};
};
};
};
sram: sram@2e000000 {
compatible = "arm,juno-sram-ns", "mmio-sram";
reg = <0x0 0x2e000000 0x0 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x2e000000 0x8000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,juno-scp-shmem";
reg = <0x0 0x200>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "arm,juno-scp-shmem";
reg = <0x200 0x200>;
};
};
pcie_ctlr: pcie-controller@40000000 {
compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
device_type = "pci";
reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
bus-range = <0 255>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
<0 0 0 2 &gic 0 0 0 137 4>,
<0 0 0 3 &gic 0 0 0 138 4>,
<0 0 0 4 &gic 0 0 0 139 4>;
msi-parent = <&v2m_0>;
status = "disabled";
};
scpi {
compatible = "arm,scpi";
mboxes = <&mailbox 1>;
shmem = <&cpu_scp_hpri>;
clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi-dvfs {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
};
scpi_clk: scpi-clk {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>;
clock-output-names = "pxlclk";
};
};
scpi_devpd: scpi-power-domains {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
};
scpi_sensors0: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
thermal-zones {
pmic {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
};
soc {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
};
big_cluster_thermal_zone: big_cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 21>;
status = "disabled";
};
little_cluster_thermal_zone: little_cluster {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 22>;
status = "disabled";
};
gpu0_thermal_zone: gpu0 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 23>;
status = "disabled";
};
gpu1_thermal_zone: gpu1 {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 24>;
status = "disabled";
};
};
/include/ "juno-clocks.dtsi"
dma@7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x7ff00000 0 0x1000>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_faxiclk>;
clock-names = "apb_pclk";
};
hdlcd@7ff50000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff50000 0 0x1000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
port {
hdlcd1_output: hdlcd1-endpoint {
remote-endpoint = <&tda998x_1_input>;
};
};
};
hdlcd@7ff60000 {
compatible = "arm,hdlcd";
reg = <0 0x7ff60000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scpi_clk 3>;
clock-names = "pxlclk";
port {
hdlcd0_output: hdlcd0-endpoint {
remote-endpoint = <&tda998x_0_input>;
};
};
};
soc_uart0: uart@7ff80000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x7ff80000 0x0 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
i2c@7ffa0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x7ffa0000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <500>;
clocks = <&soc_smc50mhz>;
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
tda998x_0_input: tda998x-0-endpoint {
remote-endpoint = <&hdlcd0_output>;
};
};
};
hdmi-transmitter@71 {
compatible = "nxp,tda998x";
reg = <0x71>;
port {
tda998x_1_input: tda998x-1-endpoint {
remote-endpoint = <&hdlcd1_output>;
};
};
};
};
ohci@7ffb0000 {
compatible = "generic-ohci";
reg = <0x0 0x7ffb0000 0x0 0x10000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_usb48mhz>;
};
ehci@7ffc0000 {
compatible = "generic-ehci";
reg = <0x0 0x7ffc0000 0x0 0x10000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_usb48mhz>;
};
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
};
memory@80000000 {
device_type = "memory";
/* last 16MB of the first memory area is reserved for secure world use by firmware */
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
<0x00000008 0x80000000 0x1 0x80000000>;
};
smb@08000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 15>;
interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
/include/ "juno-motherboard.dtsi"
};
site2: tlx@60000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x60000000 0x10000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0>;
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
};

44
arch/arm64/boot/dts/arm/juno-clocks.dtsi
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@ -1,44 +0,0 @@
/*
* ARM Juno Platform clocks
*
* Copyright (c) 2013-2014 ARM Ltd
*
* This file is licensed under a dual GPLv2 or BSD license.
*
*/
/* SoC fixed clocks */
soc_uartclk: refclk7273800hz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7273800>;
clock-output-names = "juno:uartclk";
};
soc_usb48mhz: clk48mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "clk48mhz";
};
soc_smc50mhz: clk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "smc_clk";
};
soc_refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
soc_faxiclk: refclk400mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
clock-output-names = "faxi_clk";
};

298
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
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@ -1,298 +0,0 @@
/*
* ARM Juno Platform motherboard peripherals
*
* Copyright (c) 2013-2014 ARM Ltd
*
* This file is licensed under a dual GPLv2 or BSD license.
*
*/
mb_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "juno_mb:clk24mhz";
};
mb_clk25mhz: clk25mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "juno_mb:clk25mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "juno_mb:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "juno_mb:refclk32khz";
};
motherboard {
compatible = "arm,vexpress,v2p-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
model = "V2M-Juno";
arm,hbi = <0x252>;
arm,vexpress,site = <0>;
arm,v2m-memory-map = "rs1";
mb_fixed_3v3: mcc-sb-3v3 {
compatible = "regulator-fixed";
regulator-name = "MCC_SB_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
power-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <116>;
label = "POWER";
gpios = <&iofpga_gpio0 0 0x4>;
};
home-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <102>;
label = "HOME";
gpios = <&iofpga_gpio0 1 0x4>;
};
rlock-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <152>;
label = "RLOCK";
gpios = <&iofpga_gpio0 2 0x4>;
};
vol-up-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <115>;
label = "VOL+";
gpios = <&iofpga_gpio0 3 0x4>;
};
vol-down-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <114>;
label = "VOL-";
gpios = <&iofpga_gpio0 4 0x4>;
};
nmi-button {
debounce_interval = <50>;
wakeup-source;
linux,code = <99>;
label = "NMI";
gpios = <&iofpga_gpio0 5 0x4>;
};
};
flash@0,00000000 {
/* 2 * 32MiB NOR Flash memory mounted on CS0 */
compatible = "arm,vexpress-flash", "cfi-flash";
linux,part-probe = "afs";
reg = <0 0x00000000 0x04000000>;
bank-width = <4>;
/*
* Unfortunately, accessing the flash disturbs
* the CPU idle states (suspend) and CPU
* hotplug of the platform. For this reason,
* flash hardware access is disabled by default.
*/
status = "disabled";
};
ethernet@2,00000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x00000000 0x10000>;
interrupts = <3>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
clocks = <&mb_clk25mhz>;
vdd33a-supply = <&mb_fixed_3v3>;
vddvario-supply = <&mb_fixed_3v3>;
};
usb@5,00000000 {
compatible = "nxp,usb-isp1763";
reg = <5 0x00000000 0x20000>;
bus-width = <16>;
interrupts = <4>;
};
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysctl: sysctl@020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
apbregs@010000 {
compatible = "syscon", "simple-mfd";
reg = <0x010000 0x1000>;
led0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
label = "vexpress:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
label = "vexpress:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
label = "vexpress:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "vexpress:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "vexpress:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "vexpress:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "vexpress:6";
default-state = "off";
};
led7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "vexpress:7";
default-state = "off";
};
};
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <5>;
/* cd-gpios = <&v2m_mmc_gpios 0 0>;
wp-gpios = <&v2m_mmc_gpios 1 0>; */
max-frequency = <12000000>;
vmmc-supply = <&mb_fixed_3v3>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <8>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <8>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
wdt@0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x10000>;
interrupts = <7>;
clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x10000>;
interrupts = <9>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x10000>;
interrupts = <9>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x10000>;
interrupts = <0>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
};
iofpga_gpio0: gpio@1d0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x1d0000 0x1000>;
interrupts = <6>;
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

223
arch/arm64/boot/dts/arm/juno-r1.dts
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@ -1,223 +0,0 @@
/*
* ARM Ltd. Juno Platform
*
* Copyright (c) 2015 ARM Ltd.
*
* This file is licensed under a dual GPLv2 or BSD license.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "ARM Juno development board (r1)";
compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &soc_uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&A57_0>;
};
core1 {
cpu = <&A57_1>;
};
};
cluster1 {
core0 {
cpu = <&A53_0>;
};
core1 {
cpu = <&A53_1>;
};
core2 {
cpu = <&A53_2>;
};
core3 {
cpu = <&A53_3>;
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_L2: l2-cache0 {
compatible = "cache";
};
A53_L2: l2-cache1 {
compatible = "cache";
};
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A57_0>,
<&A57_1>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>,
<&A53_1>,
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&memtimer {
status = "okay";
};
&pcie_ctlr {
status = "okay";
};
&etm0 {
cpu = <&A57_0>;
};
&etm1 {
cpu = <&A57_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};
&big_cluster_thermal_zone {
status = "okay";
};
&little_cluster_thermal_zone {
status = "okay";
};
&gpu0_thermal_zone {
status = "okay";
};
&gpu1_thermal_zone {
status = "okay";
};

223
arch/arm64/boot/dts/arm/juno-r2.dts
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@ -1,223 +0,0 @@
/*
* ARM Ltd. Juno Platform
*
* Copyright (c) 2015 ARM Ltd.
*
* This file is licensed under a dual GPLv2 or BSD license.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "ARM Juno development board (r2)";
compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &soc_uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&A72_0>;
};
core1 {
cpu = <&A72_1>;
};
};
cluster1 {
core0 {
cpu = <&A53_0>;
};
core1 {
cpu = <&A53_1>;
};
core2 {
cpu = <&A53_2>;
};
core3 {
cpu = <&A53_3>;
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A72_0: cpu@0 {
compatible = "arm,cortex-a72","arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A72_1: cpu@1 {
compatible = "arm,cortex-a72","arm,armv8";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A72_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A72_L2: l2-cache0 {
compatible = "cache";
};
A53_L2: l2-cache1 {
compatible = "cache";
};
};
pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A72_0>,
<&A72_1>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>,
<&A53_1>,
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&memtimer {
status = "okay";
};
&pcie_ctlr {
status = "okay";
};
&etm0 {
cpu = <&A72_0>;
};
&etm1 {
cpu = <&A72_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};
&big_cluster_thermal_zone {
status = "okay";
};
&little_cluster_thermal_zone {
status = "okay";
};
&gpu0_thermal_zone {
status = "okay";
};
&gpu1_thermal_zone {
status = "okay";
};

199
arch/arm64/boot/dts/arm/juno.dts
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@ -1,199 +0,0 @@
/*
* ARM Ltd. Juno Platform
*
* Copyright (c) 2013-2014 ARM Ltd.
*
* This file is licensed under a dual GPLv2 or BSD license.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "ARM Juno development board (r0)";
compatible = "arm,juno", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &soc_uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&A57_0>;
};
core1 {
cpu = <&A57_1>;
};
};
cluster1 {
core0 {
cpu = <&A53_0>;
};
core1 {
cpu = <&A53_1>;
};
core2 {
cpu = <&A53_2>;
};
core3 {
cpu = <&A53_3>;
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
};
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
clocks = <&scpi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
clocks = <&scpi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
A57_L2: l2-cache0 {
compatible = "cache";
};
A53_L2: l2-cache1 {
compatible = "cache";
};
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A57_0>,
<&A57_1>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A53_0>,
<&A53_1>,
<&A53_2>,
<&A53_3>;
};
#include "juno-base.dtsi"
};
&etm0 {
cpu = <&A57_0>;
};
&etm1 {
cpu = <&A57_1>;
};
&etm2 {
cpu = <&A53_0>;
};
&etm3 {
cpu = <&A53_1>;
};
&etm4 {
cpu = <&A53_2>;
};
&etm5 {
cpu = <&A53_3>;
};

167
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
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@ -1,167 +0,0 @@
/*
* ARM Ltd. Fast Models
*
* Architecture Envelope Model (AEM) ARMv8-A
* ARMAEMv8AMPCT
*
* RTSM_VE_AEMv8A.lisa
*/
/dts-v1/;
/memreserve/ 0x80000000 0x00010000;
/ {
model = "RTSM_VE_AEMv8A";
compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x1000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <100000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
smb@08000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
/include/ "rtsm_ve-motherboard.dtsi"
};
};

275
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
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@ -1,275 +0,0 @@
/*
* ARM Ltd. Fast Models
*
* Versatile Express (VE) system model
* Motherboard component
*
* VEMotherBoard.lisa
*/
motherboard {
arm,v2m-memory-map = "rs1";
compatible = "arm,vexpress,v2m-p1", "simple-bus";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
ranges;
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
};
v2m_video_ram: vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
};
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
iofpga@3,00000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
v2m_sysreg: sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
v2m_sysctl: sysctl@020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};
aaci@040000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
};
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>;
max-frequency = <12000000>;
vmmc-supply = <&v2m_fixed_3v3>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "mclk", "apb_pclk";
};
kmi@060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk";
};
wdt@0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
clock-names = "wdogclk", "apb_pclk";
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>;
interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk";
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
interrupts = <4>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
};
clcd@1f0000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>;
interrupt-names = "combined";
interrupts = <14>;
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
clock-names = "clcdclk", "apb_pclk";
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
memory-region = <&v2m_video_ram>;
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
port {
v2m_clcd_pads: endpoint {
remote-endpoint = <&v2m_clcd_panel>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
v2m_clcd_panel: endpoint {
remote-endpoint = <&v2m_clcd_pads>;
};
};
panel-timing {
clock-frequency = <63500127>;
hactive = <1024>;
hback-porch = <152>;
hfront-porch = <48>;
hsync-len = <104>;
vactive = <768>;
vback-porch = <23>;
vfront-porch = <3>;
vsync-len = <4>;
};
};
};
virtio_block@0130000 {
compatible = "virtio,mmio";
reg = <0x130000 0x200>;
interrupts = <42>;
};
};
v2m_fixed_3v3: v2m-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
v2m_oscclk1: oscclk1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
freq-range = <23750000 63500000>;
#clock-cells = <0>;
clock-output-names = "v2m:oscclk1";
};
reset {
compatible = "arm,vexpress-reset";
arm,vexpress-sysreg,func = <5 0>;
};
muxfpga {
compatible = "arm,vexpress-muxfpga";
arm,vexpress-sysreg,func = <7 0>;
};
shutdown {
compatible = "arm,vexpress-shutdown";
arm,vexpress-sysreg,func = <8 0>;
};
reboot {
compatible = "arm,vexpress-reboot";
arm,vexpress-sysreg,func = <9 0>;
};
dvimode {
compatible = "arm,vexpress-dvimode";
arm,vexpress-sysreg,func = <11 0>;
};
};
};

191
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
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@ -1,191 +0,0 @@
/*
* ARM Ltd. Versatile Express
*
* LogicTile Express 20MG
* V2F-1XV7
*
* Cortex-A53 (2 cores) Soft Macrocell Model
*
* HBI-0247C
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "V2F-1XV7 Cortex-A53x2 SMM";
arm,hbi = <0x247>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:38400n8";
};
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 1>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
};
gic: interrupt-controller@2c001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
smbclk: smclk {
/* SMC clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <40000000 40000000>;
#clock-cells = <0>;
clock-output-names = "smclk";
};
volt-vio {
/* VIO to expansion board above */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VIO_UP";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
volt-12v {
/* 12V from power connector J6 */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
regulator-name = "12";
regulator-always-on;
};
temp-fpga {
/* FPGA temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "FPGA";
};
};
smb@08000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
/include/ "vexpress-v2m-rs1.dtsi"
};
};

1
arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi
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@ -1 +0,0 @@
../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi

7
arch/arm64/boot/dts/broadcom/Makefile
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@ -1,7 +0,0 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

1
arch/arm64/boot/dts/broadcom/bcm2835-rpi.dtsi
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@ -1 +0,0 @@
../../../../arm/boot/dts/bcm2835-rpi.dtsi

23
arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
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@ -1,23 +0,0 @@
/dts-v1/;
#include "bcm2837.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
model = "Raspberry Pi 3 Model B";
memory {
reg = <0 0x40000000>;
};
leds {
act {
gpios = <&gpio 47 0>;
};
};
};
&uart1 {
status = "okay";
};

76
arch/arm64/boot/dts/broadcom/bcm2837.dtsi
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@ -1,76 +0,0 @@
#include "bcm283x.dtsi"
/ {
compatible = "brcm,bcm2837";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
<0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
local_intc: local_intc {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&local_intc>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
interrupts = <0>, // PHYS_SECURE_PPI
<1>, // PHYS_NONSECURE_PPI
<3>, // VIRT_PPI
<2>; // HYP_PPI
always-on;
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000d8>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000e8>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x000000f0>;
};
};
};
/* Make the BCM2835-style global interrupt controller be a child of the
* CPU-local interrupt controller.
*/
&intc {
compatible = "brcm,bcm2836-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
};

1
arch/arm64/boot/dts/broadcom/bcm283x-rpi-smsc9514.dtsi
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@ -1 +0,0 @@
../../../../arm/boot/dts/bcm283x-rpi-smsc9514.dtsi

1
arch/arm64/boot/dts/broadcom/bcm283x.dtsi
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@ -1 +0,0 @@
../../../../arm/boot/dts/bcm283x.dtsi

105
arch/arm64/boot/dts/broadcom/ns2-clock.dtsi
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@ -1,105 +0,0 @@
/*
* BSD LICENSE
*
* Copyright (c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-ns2.h>
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
lcpll_ddr: lcpll_ddr@6501d058 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ddr";
reg = <0x6501d058 0x20>,
<0x6501c020 0x4>,
<0x6501d04c 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ddr", "pcie_sata_usb",
"ddr", "ddr_ch2_unused",
"ddr_ch3_unused", "ddr_ch4_unused",
"ddr_ch5_unused";
};
lcpll_ports: lcpll_ports@6501d078 {
#clock-cells = <1>;
compatible = "brcm,ns2-lcpll-ports";
reg = <0x6501d078 0x20>,
<0x6501c020 0x4>,
<0x6501d054 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll_ports", "wan", "rgmii",
"ports_ch2_unused",
"ports_ch3_unused",
"ports_ch4_unused",
"ports_ch5_unused";
};
genpll_scr: genpll_scr@6501d098 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-scr";
reg = <0x6501d098 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_scr", "scr", "fs",
"audio_ref", "scr_ch3_unused",
"scr_ch4_unused", "scr_ch5_unused";
};
iprocmed: iprocmed {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
iprocslow: iprocslow {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
genpll_sw: genpll_sw@6501d0c4 {
#clock-cells = <1>;
compatible = "brcm,ns2-genpll-sw";
reg = <0x6501d0c4 0x32>,
<0x6501c020 0x4>,
<0x6501d044 0x4>;
clocks = <&osc>;
clock-output-names = "genpll_sw", "rpe", "250", "nic",
"chimp", "port", "sdio";
};

189
arch/arm64/boot/dts/broadcom/ns2-svk.dts
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@ -1,189 +0,0 @@
/*
* BSD LICENSE
*
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "ns2.dtsi"
/ {
model = "Broadcom NS2 SVK";
compatible = "brcm,ns2-svk", "brcm,ns2";
aliases {
serial0 = &uart3;
serial1 = &uart0;
serial2 = &uart1;
serial3 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "earlycon=uart8250,mmio32,0x66130000";
};
memory {
device_type = "memory";
reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
};
};
&pci_phy0 {
status = "ok";
};
&pci_phy1 {
status = "ok";
};
&pcie0 {
status = "ok";
};
&pcie4 {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};
&uart0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&uart2 {
status = "ok";
};
&uart3 {
status = "ok";
};
&ssp0 {
status = "ok";
slic@0 {
compatible = "silabs,si3226x";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha = <1>;
spi-cpol = <1>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};
&ssp1 {
status = "ok";
at25@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
spi-cpha = <1>;
spi-cpol = <1>;
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
};
};
&sata_phy0 {
status = "ok";
};
&sata_phy1 {
status = "ok";
};
&sata {
status = "ok";
};
&sdio0 {
status = "ok";
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <16>;
brcm,nand-oob-sector-size = <16>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
reg = <0x10>;
};
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

571
arch/arm64/boot/dts/broadcom/ns2.dtsi
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@ -1,571 +0,0 @@
/*
* BSD LICENSE
*
* Copyright (c) 2015 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/memreserve/ 0x81000000 0x00200000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>
/ {
compatible = "brcm,ns2";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
A57_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
A57_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
A57_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 2>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
A57_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 3>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
};
CLUSTER0_L2: l2-cache@000 {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A57_0>,
<&A57_1>,
<&A57_2>,
<&A57_3>;
};
pcie0: pcie@20020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x20020000 0 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
brcm,pcie-ob;
brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x00000000>;
brcm,pcie-ob-window-size = <256>;
status = "disabled";
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
<GIC_SPI 278 IRQ_TYPE_NONE>,
<GIC_SPI 279 IRQ_TYPE_NONE>,
<GIC_SPI 280 IRQ_TYPE_NONE>;
brcm,num-eq-region = <1>;
brcm,num-msi-msg-region = <1>;
};
};
pcie4: pcie@50020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x50020000 0 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
linux,pci-domain = <4>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
brcm,pcie-ob;
brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x30000000>;
brcm,pcie-ob-window-size = <256>;
status = "disabled";
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
<GIC_SPI 302 IRQ_TYPE_NONE>,
<GIC_SPI 303 IRQ_TYPE_NONE>,
<GIC_SPI 304 IRQ_TYPE_NONE>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
#include "ns2-clock.dtsi"
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&iprocslow>;
clock-names = "apb_pclk";
};
smmu: mmu@64000000 {
compatible = "arm,mmu-500";
reg = <0x64000000 0x40000>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
mmu-masters;
};
pinctrl: pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
<0x660a0028 0x04>,
<0x660009b0 0x40>;
};
gpio_aon: gpio@65024800 {
compatible = "brcm,iproc-gpio";
reg = <0x65024800 0x50>,
<0x65024008 0x18>;
ngpios = <6>;
#gpio-cells = <2>;
gpio-controller;
};
gic: interrupt-controller@65210000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x65210000 0x1000>,
<0x65220000 0x1000>,
<0x65240000 0x2000>,
<0x65260000 0x1000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_HIGH)>;
};
cci@65590000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x65590000 0x1000>;
ranges = <0 0x65590000 0x10000>;
pmu@9000 {
compatible = "arm,cci-400-pmu,r1",
"arm,cci-400-pmu";
reg = <0x9000 0x4000>;
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
};
};
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;
clocks = <&osc>;
#pwm-cells = <3>;
status = "disabled";
};
mdio_mux_iproc: mdio-mux@6602023c {
compatible = "brcm,mdio-mux-iproc";
reg = <0x6602023c 0x14>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
pci_phy0: pci-phy@0 {
compatible = "brcm,ns2-pcie-phy";
reg = <0x0>;
#phy-cells = <0>;
status = "disabled";
};
};
mdio@7 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
pci_phy1: pci-phy@0 {
compatible = "brcm,ns2-pcie-phy";
reg = <0x0>;
#phy-cells = <0>;
status = "disabled";
};
};
mdio@10 {
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
};
};
timer0: timer@66030000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66030000 0x1000>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer1: timer@66040000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66040000 0x1000>;
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer2: timer@66050000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66050000 0x1000>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer3: timer@66060000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66060000 0x1000>;
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
i2c0: i2c@66080000 {
compatible = "brcm,iproc-i2c";
reg = <0x66080000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
wdt0: watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "wdogclk", "apb_pclk";
};
gpio_g: gpio@660a0000 {
compatible = "brcm,iproc-gpio";
reg = <0x660a0000 0x50>;
ngpios = <32>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
};
i2c1: i2c@660b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x660b0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: serial@66100000 {
compatible = "snps,dw-apb-uart";
reg = <0x66100000 0x100>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@66110000 {
compatible = "snps,dw-apb-uart";
reg = <0x66110000 0x100>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@66120000 {
compatible = "snps,dw-apb-uart";
reg = <0x66120000 0x100>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@66130000 {
compatible = "snps,dw-apb-uart";
reg = <0x66130000 0x100>;
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
status = "disabled";
};
ssp0: ssp@66180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66180000 0x1000>;
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "spiclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssp1: ssp@66190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66190000 0x1000>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "spiclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hwrng: hwrng@66220000 {
compatible = "brcm,iproc-rng200";
reg = <0x66220000 0x28>;
};
sata_phy: sata_phy@663f0100 {
compatible = "brcm,iproc-ns2-sata-phy";
reg = <0x663f0100 0x1f00>,
<0x663f004c 0x10>;
reg-names = "phy", "phy-ctrl";
#address-cells = <1>;
#size-cells = <0>;
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
status = "disabled";
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
status = "disabled";
};
};
sata: ahci@663f2000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x663f2000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
phy-names = "sata-phy";
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
phy-names = "sata-phy";
};
};
sdio0: sdhci@66420000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66420000 0x100>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
status = "disabled";
};
sdio1: sdhci@66430000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66430000 0x100>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
status = "disabled";
};
nand: nand@66460000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x66460000 0x600>,
<0x67015408 0x600>,
<0x66460f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
};
};
};

33
arch/arm64/boot/dts/broadcom/vulcan-eval.dts
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@ -1,33 +0,0 @@
/*
* dts file for Broadcom (BRCM) Vulcan Evaluation Platform
*
* Copyright (c) 2013-2016 Broadcom
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/dts-v1/;
#include "vulcan.dtsi"
/ {
model = "Broadcom Vulcan Eval Platform";
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
memory {
device_type = "memory";
reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
<0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

147
arch/arm64/boot/dts/broadcom/vulcan.dtsi
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@ -1,147 +0,0 @@
/*
* dtsi file for Broadcom (BRCM) Vulcan processor
*
* Copyright (c) 2013-2016 Broadcom
* Author: Zi Shen Lim <zlim@broadcom.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Broadcom Vulcan";
compatible = "brcm,vulcan-soc";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
/* just 4 cpus now, 128 needed in full config */
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu@0 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "brcm,vulcan", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
gic: interrupt-controller@400080000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
<0x04 0x01000000 0x0 0x1000000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gicits: gic-its@40010000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
pmu {
compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
};
clk125mhz: uart_clk125mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "clk125mhz";
};
pci {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#interrupt-cells = <1>;
#address-cells = <3>;
#size-cells = <2>;
/* ECAM at 0x3000_0000 - 0x4000_0000 */
reg = <0x0 0x30000000 0x0 0x10000000>;
reg-names = "PCI ECAM";
/*
* PCI ranges:
* IO no supported
* MEM 0x4000_0000 - 0x6000_0000
* MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
*/
ranges =
<0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map =
/* addr pin ic icaddr icintr */
<0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&gicits>;
dma-coherent;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
uart0: serial@402020000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x04 0x02020000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk125mhz>;
clock-names = "apb_pclk";
};
};
};

5
arch/arm64/boot/dts/cavium/Makefile
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@ -1,5 +0,0 @@
dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

67
arch/arm64/boot/dts/cavium/thunder-88xx.dts
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@ -1,67 +0,0 @@
/*
* Cavium Thunder DTS file - Thunder board description
*
* Copyright (C) 2014, Cavium Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "thunder-88xx.dtsi"
/ {
model = "Cavium ThunderX CN88XX board";
compatible = "cavium,thunder-88xx";
aliases {
serial0 = &uaa0;
serial1 = &uaa1;
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x80000000>;
};
};

415
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
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@ -1,415 +0,0 @@
/*
* Cavium Thunder DTS file - Thunder SoC description
*
* Copyright (C) 2014, Cavium Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this library; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
compatible = "cavium,thunder-88xx";
interrupt-parent = <&gic0>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@000 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x000>;
enable-method = "psci";
};
cpu@001 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x001>;
enable-method = "psci";
};
cpu@002 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x002>;
enable-method = "psci";
};
cpu@003 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x003>;
enable-method = "psci";
};
cpu@004 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x004>;
enable-method = "psci";
};
cpu@005 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x005>;
enable-method = "psci";
};
cpu@006 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x006>;
enable-method = "psci";
};
cpu@007 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x007>;
enable-method = "psci";
};
cpu@008 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x008>;
enable-method = "psci";
};
cpu@009 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x009>;
enable-method = "psci";
};
cpu@00a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00a>;
enable-method = "psci";
};
cpu@00b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00b>;
enable-method = "psci";
};
cpu@00c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00c>;
enable-method = "psci";
};
cpu@00d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00d>;
enable-method = "psci";
};
cpu@00e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00e>;
enable-method = "psci";
};
cpu@00f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x00f>;
enable-method = "psci";
};
cpu@100 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu@101 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu@102 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu@103 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
};
cpu@104 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x104>;
enable-method = "psci";
};
cpu@105 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x105>;
enable-method = "psci";
};
cpu@106 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x106>;
enable-method = "psci";
};
cpu@107 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x107>;
enable-method = "psci";
};
cpu@108 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x108>;
enable-method = "psci";
};
cpu@109 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x109>;
enable-method = "psci";
};
cpu@10a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10a>;
enable-method = "psci";
};
cpu@10b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10b>;
enable-method = "psci";
};
cpu@10c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10c>;
enable-method = "psci";
};
cpu@10d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10d>;
enable-method = "psci";
};
cpu@10e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10e>;
enable-method = "psci";
};
cpu@10f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x10f>;
enable-method = "psci";
};
cpu@200 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu@201 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x201>;
enable-method = "psci";
};
cpu@202 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x202>;
enable-method = "psci";
};
cpu@203 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x203>;
enable-method = "psci";
};
cpu@204 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x204>;
enable-method = "psci";
};
cpu@205 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x205>;
enable-method = "psci";
};
cpu@206 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x206>;
enable-method = "psci";
};
cpu@207 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x207>;
enable-method = "psci";
};
cpu@208 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x208>;
enable-method = "psci";
};
cpu@209 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x209>;
enable-method = "psci";
};
cpu@20a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20a>;
enable-method = "psci";
};
cpu@20b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20b>;
enable-method = "psci";
};
cpu@20c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20c>;
enable-method = "psci";
};
cpu@20d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20d>;
enable-method = "psci";
};
cpu@20e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20e>;
enable-method = "psci";
};
cpu@20f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
reg = <0x0 0x20f>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
};
pmu {
compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
interrupts = <1 7 4>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "refclk50mhz";
};
gic0: interrupt-controller@8010,00000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
<0x8010 0x80000000 0x0 0x600000>; /* GICR */
interrupts = <1 9 0xf04>;
its: gic-its@8010,00020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x8010 0x20000 0x0 0x200000>;
};
};
uaa0: serial@87e0,24000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x24000000 0x0 0x1000>;
interrupts = <1 21 4>;
clocks = <&refclk50mhz>;
clock-names = "apb_pclk";
};
uaa1: serial@87e0,25000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x25000000 0x0 0x1000>;
interrupts = <1 22 4>;
clocks = <&refclk50mhz>;
clock-names = "apb_pclk";
};
};
};

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